> -----Original Message----- > From: Intel-wired-lan <[email protected]> On Behalf Of > Arkadiusz Kubalewski > Sent: 22 April 2025 21:32 > To: [email protected] > Cc: [email protected]; Kubalewski, Arkadiusz > <[email protected]>; Kitszel, Przemyslaw > <[email protected]> > Subject: [Intel-wired-lan] [PATCH iwl-next v5 1/3] ice: redesign dpll > sma/u.fl pins control > > DPLL-enabled E810 NIC driver provides user with list of input and output > pins. Hardware internal design impacts user control over SMA and U.FL pins. > Currently end-user view on those dpll pins doesn't provide any layer of > abstraction. On the hardware level SMA and U.FL pins are tied together due to > existence of direction control logic for each pair: > - SMA1 (bi-directional) and U.FL1 (only output) > - SMA2 (bi-directional) and U.FL2 (only input) The user activity on each pin > of the pair may impact the state of the other. > > Previously all the pins were provided to the user as is, without the control > over SMA pins direction. > > Introduce a software controlled layer of abstraction over external board > pins, instead of providing the user with access to raw pins connected to the > dpll: > - new software controlled SMA and U.FL pins, > - callback operations directing user requests to corresponding hardware pins according to the runtime configuration, > - ability to control SMA pins direction. > > Reviewed-by: Przemek Kitszel <[email protected]> > Signed-off-by: Arkadiusz Kubalewski <[email protected]> > --- > v5: > - stop pins unregister for not present SW pins @E810-LOM NIC. > --- > drivers/net/ethernet/intel/ice/ice_dpll.c | 927 +++++++++++++++++++- > drivers/net/ethernet/intel/ice/ice_dpll.h | 23 +- > drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 1 + > 3 files changed, 936 insertions(+), 15 deletions(-) >
Tested-by: Rinitha S <[email protected]> (A Contingent worker at Intel)
