> -----Original Message----- > From: Intel-wired-lan <[email protected]> On Behalf Of > Arkadiusz Kubalewski > Sent: 22 April 2025 21:32 > To: [email protected] > Cc: [email protected]; Kolacinski, Karol <[email protected]>; > Olech, Milena <[email protected]>; Kubalewski, Arkadiusz > <[email protected]> > Subject: [Intel-wired-lan] [PATCH iwl-next v5 2/3] ice: change SMA pins to > SDP in PTP API > > From: Karol Kolacinski <[email protected]> > > This change aligns E810 PTP pin control to all other products. > > Currently, SMA/U.FL port expanders are controlled together with SDP pins > connected to 1588 clock. To align this, separate this control by exposing > only SDP20..23 pins in PTP API on adapters with DPLL. > > Clear error for all E810 on absent NVM pin section or other errors to allow > proper initialization on SMA E810 with NVM section. > > Use ARRAY_SIZE for pin array instead of internal definition. > > Reviewed-by: Milena Olech <[email protected]> > Signed-off-by: Karol Kolacinski <[email protected]> > Signed-off-by: Arkadiusz Kubalewski <[email protected]> > --- > v5: > - no change. > --- > drivers/net/ethernet/intel/ice/ice_ptp.c | 254 ++++------------------- > drivers/net/ethernet/intel/ice/ice_ptp.h | 3 - > 2 files changed, 39 insertions(+), 218 deletions(-) >
Tested-by: Rinitha S <[email protected]> (A Contingent worker at Intel)
