From: Karol Kolacinski <[email protected]> To ensure proper operation, wait for 10 to 20 microseconds before enabling TSPLL.
Adjust wait time after enabling TSPLL from 1-5 ms to 1-2 ms. Those values are empirical and tested on multiple HW configurations. Reviewed-by: Milena Olech <[email protected]> Signed-off-by: Karol Kolacinski <[email protected]> --- drivers/net/ethernet/intel/ice/ice_tspll.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/intel/ice/ice_tspll.c b/drivers/net/ethernet/intel/ice/ice_tspll.c index e7b44e703d7c0966414e119f861ee1ab165d9293..abd9f4ff2f5563e35dd8e8fa551eb944d8f5802a 100644 --- a/drivers/net/ethernet/intel/ice/ice_tspll.c +++ b/drivers/net/ethernet/intel/ice/ice_tspll.c @@ -261,6 +261,9 @@ static int ice_tspll_cfg_e82x(struct ice_hw *hw, enum ice_tspll_freq clk_freq, if (err) return err; + /* Wait to ensure everything is stable */ + usleep_range(10, 20); + /* Finally, enable the PLL */ r24 |= ICE_CGU_R23_R24_TSPLL_ENABLE; @@ -268,8 +271,8 @@ static int ice_tspll_cfg_e82x(struct ice_hw *hw, enum ice_tspll_freq clk_freq, if (err) return err; - /* Wait to verify if the PLL locks */ - usleep_range(1000, 5000); + /* Wait at least 1 ms to verify if the PLL locks */ + usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC); err = ice_read_cgu_reg(hw, ICE_CGU_RO_BWM_LF, &val); if (err) @@ -445,6 +448,9 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq, if (err) return err; + /* Wait to ensure everything is stable */ + usleep_range(10, 20); + /* Finally, enable the PLL */ r23 |= ICE_CGU_R23_R24_TSPLL_ENABLE; @@ -452,8 +458,8 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq, if (err) return err; - /* Wait to verify if the PLL locks */ - usleep_range(1000, 5000); + /* Wait at least 1 ms to verify if the PLL locks */ + usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC); err = ice_read_cgu_reg(hw, ICE_CGU_RO_LOCK, &val); if (err) -- 2.48.1.397.gec9d649cc640
