> -----Original Message----- > From: Jacob Keller <[email protected]> > Sent: Friday, September 25, 2026 4:57 PM > To: Intel Wired LAN <[email protected]>; Machnikowski, Maciej > <[email protected]>; Keller, Jacob E <[email protected]>; > Korba, Przemyslaw <[email protected]>; Nguyen, Anthony L > <[email protected]>; Nitka, Grzegorz <[email protected]>; > Kubalewski, Arkadiusz <[email protected]> > Cc: Keller, Jacob E <[email protected]>; Machnikowski, Maciej > <[email protected]> > Subject: [PATCH iwl-net v3 10/15] ice: E825: perform a soft reset when > starting the PHY timer > > To ensure that the E825 PHY timer begins in a clean state, initiate a PHY > soft reset prior to programming the PHY. This ensures that we clear any > outstanding Tx timestamp memory, and ensures that the PHY internal state > including its timestamp counter has been reset. > > Note that despite the name, this PHY soft reset only impacts the timer block > of the PHY, and not its regular Tx/Rx functionality. Additionally, many > configuration registers such as the PHY_REG_TS_INT_CONFIG and > PHY_REG_TX_OFFSET_READY are not reset. > > Fixes: 7cab44f1c35f ("ice: Introduce ETH56G PHY model for E825C products") > Reviewed-by: Maciek Machnikowski <[email protected]> > Signed-off-by: Jacob Keller <[email protected]> > --- > drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 12 +++++++++--- > 1 file changed, 9 insertions(+), 3 deletions(-)
Tested-by: Alexander Nowlin <[email protected]>
