Ah.  I probably should have read the PWM docs a little closer.  I guess I 
can start writing code since I’m in “waiting for shipping-land”.

Is there much penalty for 32 bit math?

When I enable “Edge aligned PWM” with the interrupt flag on, is the first 
interrupt actually the very first sync (of the initial values loaded into 
OCxR prior to enable)?  Or am I off-by-one here?


Pseudocode:

#define NR_CHANNELS 8

#define FRAME_PERIOD (frame_period_ns/clk_period_ns)

#define PULSE_WIDTH (pulse_width_ns/clk_period_ns)

unsigned long clk_period_ns = 500;  // 2MHz; max period is ~32mS

unsigned long frame_period_ns = 22000000;  // or NR_CHANNELS * 2ms + 4ms?

unsigned long pulse_width_ns = 500000; //  0.5ms

unsigned int idx;

unsigned int acc; // accumulator

unsigned int pulse_period[NR_CHANNELS];

setup() {

setup stuff;

idx = 0;

acc = 0;

OC1R = PULSE_WIDTH;

OC1RS = pulse_period[idx];

enable PWM;

}

OC1_int() {

// width/period registers are buffered and will be loaded on next sync

if (idx >= NR_CHANNELS) {

 idx = 0;

 acc = 0;

}

else {

 acc += pulse_period[idx++];  //  Am I accumulating an error too?

}

if (idx < NR_CHANNELS) {

 OC1RS = pulse_period[idx];

}

else if (idx == NR_CHANNELS) {

 OC1RS = FRAME_PERIOD - acc;

} // You're watching the "Pad Channel"

}






On Thursday, January 23, 2014 11:27:58 AM UTC-6, Ytai wrote:
>
> This has not yet been implemented. You don't need a timer I believe as the 
> OC modules have dedicated timers and in PWM mode will have shadow registers 
> for updating the duration with no jitter. 500us is plenty of time at 16MHz 
> if you use a high interrupt priority.
> On Jan 23, 2014 12:02 AM, "GoatZilla" <[email protected] <javascript:>> 
> wrote:
>
>> I noticed there was an earlier thread about PPM output being a 
>> possibility, but I don't see it being implemented yet.  Am I reading that 
>> right?
>>
>> It does look like it's possible to do with the hardware compare (is 
>> Timer2 still free?), as long as the interrupts get serviced within the 
>> shortest pulse timing...   Which is a ~500uS pulse with 500uS until next 
>> pulse.
>>
>> That sounds kind of tight with the way the double comparator only 
>> interrupts on the falling edge, so maybe two single comparators -- one for 
>> all the rising toggles, and one for all the falling toggles?  Or perhaps 
>> more?
>>
>>
>>
>>
>>
>>
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