Comments inline...

On Sunday, February 1, 2015 at 1:15:12 AM UTC-5, Ytai wrote:
>
> Thanks for your help. Inline.
>
> <[email protected] <javascript:>> wrote:
>
>> Ytai,
>> thanks for the link.  I'm glad to see this is still active.
>> I'm surprised you've narrowed it down to Load transients, since you had 
>> previously narrowed it down to spikes on Vin, and suspected long 
>> (inductive) power cables.
>>
>
> We've previously observed voltage surges exceeding (for a microsecond or 
> so) the maximum rated input voltage. Since there were no other deviations 
> from the specs, we have attributed the failures to those surges. Regardless 
> of whether or not this was *the* problem, it is definitely *a* problem, 
> thus we have revved the board to include a protection circuit for this 
> case. After having verified that the surged are gone, we continued our 
> tests to verify that the problem has gone and discovered that it hasn't. 
> Moreover, we were able to demonstrate that we are presumably able to get 
> the TPS to fail without exceeding its maximum ratings. We are trying to 
> gather more data as requested by the TI engineers to find the cause and the 
> cure.
>
>
>> I have three suggestions, in case you have the ability to test different 
>> scenarios.
>>
>> a) this one is a long shot, but it's easy, so could be worth a try.  The 
>> recommended design has a 0.1uF cap on Vin.  I don't know how this could 
>> cause the failure, unless there were a weird resonance building up inside 
>> the chip, which could be mitigated by the high-freq cap.
>>
>
> Good point. I can see why this might explain the failure. I'll try that.
>  
>
>>
>> b) I've had numerous bad experiences with switching supplies running at 
>> high frequencies. They are very sensitive to layout and load transients.  
>> I'm curious if the failure would occur at the low frequency setting.  To 
>> test this, connect FSW to PG or Vout.  Pretty tough with the QFN on IOIO, 
>> but maybe you have another vehicle to test it on.
>>
>
> I don't have a PCB where that's possible. I'm also not sure what I'll do 
> with this information if I know. I'm been pretty careful about layout as 
> I'm very well aware of how tricky it can be (learned the hard way...), but 
> obviously fast switching circuits have a lot of advantages (much smaller / 
> cheaper passives).
>  
>

Well, the 'what you would do', would be to choose the lower frequency 
setting on a future version of the board.  Too bad there's no easy way to 
test it.
 

>
>> c) Although it should not be required for this type of synchronous buck 
>> converter, The fact that the output drops might indicate the low-side 
>> output FET has blown closed.  I also seem to remember the measured 
>> resistance between SW and GND was very low on a failed device.  That being 
>> the case, it might be worth trying to protect that FET with a Zener, so 
>> that any voltage transients arising from abrupt changes in current through 
>> the inductor are clamped.
>>
>
> If you're referring to the graph posted on the TI forum, to me it looks 
> like the output capacitor being drained by the load as opposed to a hard 
> pull-down by a blown low-side FET. Zeners are not usually effective for 
> such protection, but rather two Schottkys (GND to SW, SW to Vin), but since 
> the datasheet doesn't call for them, I'm assuming the body diodes of the 
> FET and/or the synchronous operation of the high-side/low-side FET doesn't 
> require them.
>

I should have said Schottkys, not a Zener.  Did TI ever do a failure 
analysis of a failed part for you?  We really need to know if it's the 
input side or the output side that suffered the electrical stress.  Did you 
ever measure the resistance between SW and GND on a failed part?
As for the body diodes, they may have become the current path in the case 
where the low-side FET didn't turn on as quickly as it should.  The idea is 
that the external Schottky could give an alternate path for the current, 
just until that lower FET turns on.

 

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