On 10/30/2014 08:04 PM, Terje Bergström wrote:
On 30.10.2014 12:22, Alexandre Courbot wrote:
So should I understand that the GPU group is for addresses without bit
34 set (hence forcibly disabled) while GPUB is used when that bit is
set? Or is it something else?
That's exactly correct. And only GPUB can be programmed to be SMMU
translated.
Great, thanks for confirming!
Thierry, how do you want to address this? We could change the register
for the GPU group, or (maybe preferable if we want to reflect the actual
hardware state) add the GPUB group. I don't know if that would be easy
though since we would have the problem of the gpusrd and gpuswr clients
ownership (seems like they would belong to both groups?)
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