>> The driver intend to support up to 3 instances. It doesn't really mandate >> that all three instances be present in same DT node. >> Each mmio aperture in "reg" property is an instance here. reg = >> <inst0_base, size>, <inst1_base, size>, <inst2_base, size>; The reg can have >> all three or less and driver just configures based on reg and it works fine.
>So it sounds like we need at least 2 SMMUs (for non-iso and iso) but we have >up to 3 (for Tegra194). So the question is do we have a use-case where we only >use 2 and not 3? If not, then it still seems that we should require that all 3 >are present. It can be either 2 SMMUs (for non-iso) or 3 SMMUs (for non-iso and iso). Let me fail the one instance case as it can use regular arm smmu implementation and don't need nvidia implementation explicitly. >The other problem I see here is that currently the arm-smmu binding defines >the 'reg' with a 'maxItems' of 1, whereas we have 3. I believe that this will >get caught by the 'dt_binding_check' when we try to populate the binding. Thanks for pointing it out! Will update the binding doc. -KR -- nvpublic _______________________________________________ iommu mailing list firstname.lastname@example.org https://lists.linuxfoundation.org/mailman/listinfo/iommu