From: Thierry Reding <[email protected]> On NVIDIA SoC's the ARM SMMU needs to interact with the memory controller in order to map memory clients to the corresponding stream IDs. Document how the nvidia,memory-controller property can be used to achieve this.
Signed-off-by: Thierry Reding <[email protected]> --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index f66a3effba73..cf32a7955475 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -155,6 +155,12 @@ properties: power-domains: maxItems: 1 + nvidia,memory-controller: + description: A phandle to the memory controller on NVIDIA Tegra186 + and later SoCs. The memory controller needs to be programmed with + a mapping of memory client IDs to ARM SMMU stream IDs. + $ref: /schemas/types.yaml#/definitions/phandle + required: - compatible - reg @@ -177,6 +183,9 @@ allOf: reg: minItems: 1 maxItems: 2 + + required: + - nvidia,memory-controller else: properties: reg: -- 2.33.1 _______________________________________________ iommu mailing list [email protected] https://lists.linuxfoundation.org/mailman/listinfo/iommu
