You basically ask the world to be simpler. I wish it would be simpler, but
it's not :)

AVX512 is umbrella name for the set of ISA extensions, which work with 512
bit registers. https://en.wikipedia.org/wiki/AVX-512 explains it in more
details.

KNL (Xeon Phi x200, code name Knights Landing), the latest generation of
Xeon Phi available on the market, is the first hardware, which supports
AVX512 instructions. It implements the following set of instructions:
 AVX512 F, CDI, ERI and PFI.

SKX (Xeon processor line based on architecture codename Skylake, which
supports AVX512, the platform is also known as "Purley") will appear on the
market after KNL and will feature AVX512 F, CDI, BW, DQ and VL. Note that
it's not Xeon Phi, it's "regular" Xeons.

Subsequent generations will have other sets on AVX512 instructions.

So, from practical point of view, we care about real target hardware we are
going to use. In nearest future it will be KNL and SKX. So the avx512knl
and avx512skx targets.

Hope this explanation helps understand our reasoning behind avx512knl and
avx512skx targets.

Dmitry.

On Fri, Oct 21, 2016 at 5:15 AM, Morten Mikkelsen <[email protected]>
wrote:

> I have a question regarding the documentation on avx512knl and avx512skx.
>
> Is there are summary/description somewhere on why these are separate
> targets (as opposed to one isa) ie. what's the delta isa between the two.
> Also the documentation on avx512skx says simply "future Xeon CPUs". What
> does this mean exactly? Knights Mill? Knights Hill? Both? Others?
> I think it would be great if as an option we could simply use avx512 as a
> target and this would include all supported instances of avx512 in the
> binary.
>
>
> Cheers,
>
> Morten.
>
>
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