I agree. I wasn't trying to justify this feature but rather argue against it based upon my experience with a compiler that already supports it.
As for AVX-512 being limited to the server market, https://ark.intel.com/products/123613/Intel-Core-i9-7900X-Processor-13_75M-Cache-up-to-4_30-GHz is the exception that proves the rule, which is to say, I agree that folks who target AVX-512 are likely to do so in an implementation/uarch-specific. Jeff On Tue, May 30, 2017 at 4:20 PM, Dmitry Babokin <[email protected]> wrote: > Jeff, > > This is definitely an option. But from practical point of view, I don't > think it has enough ROI - mostly because AVX512 is currently for servers > only and in this segment people (who also care about performance) prefer to > compile for their particular platform. > > Though, if anyone is willing to implement avx512f target, I don't mind > reviewing merging the changes. > > Dmitry. > > On Sat, May 27, 2017 at 4:19 PM, Jeff Hammond <[email protected]> > wrote: > >> One can imagine supporting the union ISA of KNL and SKX (AVX-512 F+CD) >> along the lines of the Intel compiler flag -xCOMMON-AVX512, since the >> largest performance benefit of AVX-512 comes from F+CD. >> >> However, as a cautionary note for ISPC users/developers, the >> microarchitectural differences between KNL and SKX are nontrivial and >> generating code to the union ISA may lead to universally suboptimal >> performance in some cases (in other cases, it has a negligible effect). >> >> I don't know if Clang or ISPC support fat binaries, but that's a better >> option than the union ISA if available, although it obviously has an impact >> on code size and introduces runtime dispatch overhead. >> >> Jeff >> >> On Friday, October 21, 2016 at 6:50:02 AM UTC-7, Dmitry Babokin wrote: >>> >>> You basically ask the world to be simpler. I wish it would be simpler, >>> but it's not :) >>> >>> AVX512 is umbrella name for the set of ISA extensions, which work with >>> 512 bit registers. https://en.wikipedia.org/wiki/AVX-512 explains it in >>> more details. >>> >>> KNL (Xeon Phi x200, code name Knights Landing), the latest generation of >>> Xeon Phi available on the market, is the first hardware, which supports >>> AVX512 instructions. It implements the following set of instructions: >>> AVX512 F, CDI, ERI and PFI. >>> >>> SKX (Xeon processor line based on architecture codename Skylake, which >>> supports AVX512, the platform is also known as "Purley") will appear on the >>> market after KNL and will feature AVX512 F, CDI, BW, DQ and VL. Note that >>> it's not Xeon Phi, it's "regular" Xeons. >>> >>> Subsequent generations will have other sets on AVX512 instructions. >>> >>> So, from practical point of view, we care about real target hardware we >>> are going to use. In nearest future it will be KNL and SKX. So the >>> avx512knl and avx512skx targets. >>> >>> Hope this explanation helps understand our reasoning behind avx512knl >>> and avx512skx targets. >>> >>> Dmitry. >>> >>> On Fri, Oct 21, 2016 at 5:15 AM, Morten Mikkelsen <[email protected]> >>> wrote: >>> >>>> I have a question regarding the documentation on avx512knl and >>>> avx512skx. >>>> >>>> Is there are summary/description somewhere on why these are separate >>>> targets (as opposed to one isa) ie. what's the delta isa between the two. >>>> Also the documentation on avx512skx says simply "future Xeon CPUs". >>>> What does this mean exactly? Knights Mill? Knights Hill? Both? Others? >>>> I think it would be great if as an option we could simply use avx512 as >>>> a target and this would include all supported instances of avx512 in the >>>> binary. >>>> >>>> >>>> Cheers, >>>> >>>> Morten. >>>> >>>> >>>> -- >>>> You received this message because you are subscribed to the Google >>>> Groups "Intel SPMD Program Compiler Users" group. >>>> To unsubscribe from this group and stop receiving emails from it, send >>>> an email to [email protected]. >>>> For more options, visit https://groups.google.com/d/optout. >>>> >>> >>> -- >> You received this message because you are subscribed to the Google Groups >> "Intel SPMD Program Compiler Users" group. >> To unsubscribe from this group and stop receiving emails from it, send an >> email to [email protected]. >> For more options, visit https://groups.google.com/d/optout. >> > > -- > You received this message because you are subscribed to a topic in the > Google Groups "Intel SPMD Program Compiler Users" group. > To unsubscribe from this topic, visit https://groups.google.com/d/ > topic/ispc-users/mKPq0SJnDWk/unsubscribe. > To unsubscribe from this group and all its topics, send an email to > [email protected]. > For more options, visit https://groups.google.com/d/optout. > -- Jeff Hammond [email protected] http://jeffhammond.github.io/ -- You received this message because you are subscribed to the Google Groups "Intel SPMD Program Compiler Users" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
