> -----Original Message-----
> From: [email protected] [mailto:[email protected]] On
> Behalf Of Bityutskiy, Artem
> Sent: Friday, October 11, 2013 12:41 PM
> To: Lynch, Rusty; Barnes, Jesse
> Cc: [email protected]
> Subject: Re: New kernel results in our HDMI display showing up as HDMI2
> instead of HDMI1
>
> [CCing Jesse, as I am talking about his patch]
>
> On Thu, 2013-10-10 at 19:04 -0700, Rusty Lynch wrote:
> > I went ahead and pulled in your kernel update into the release project
> > and now see that the display was once showing up as HDMI1 is now
> > showing up as HDMI2.
>
> OK, this is because of the HDMI3 enabling patch:
>
> https://review.tizen.org/git/?p=profile/ivi/kernel-x86-
> ivi.git;a=commit;h=a18e6aeb05162a53b5f23a0eaba72e40884753fc
>
> Before this patch, the port register order was (simplified):
>
> DP
> HDMIB
>
> After this patch the order is:
>
> HDMIC
> DP
> HDMIB
>
> BB have only HDMIB connector, HDMIC is on the chip, but there is no
> connector.
>
> As you see, with this patch HDMIB is registered after HDMIC, which means
> that the dirver will name it "HDMI-2", while before this patch it was "HDMI-
> 1".
>
> To put it differently, the numbering depends on the order the driver
> registers ports.
Would this (silly/naïve) patch restore the original order yet preserving the
fact we also want to enable HDMIC if a connector is attached to it?
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index f103b68..a5da637 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9045,20 +9045,20 @@ static void intel_setup_outputs(struct drm_device *dev)
intel_dp_init(dev, PCH_DP_D, PORT_D);
} else if (IS_VALLEYVIEW(dev)) {
/* Check for built-in panel first. Shares lanes with HDMI on
SDVOC */
- if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
- intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
- PORT_C);
- if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
- intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
- PORT_C);
- }
-
if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
PORT_B);
if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B,
PORT_B);
}
+
+ if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
+ intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
+ PORT_C);
+ if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
+ intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
+ PORT_C);
+ }
} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
bool found = false;
I don't have such system to try it out but happy to push it to Gerrit if you
want to try/review/accept it.
Geoffroy
Intel Corporation NV/SA
Kings Square, Veldkant 31
2550 Kontich
RPM (Bruxelles) 0415.497.718.
Citibank, Brussels, account 570/1031255/09
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