On Friday 17 November 2006 23:20, Hans Verkuil wrote: Here's my second attempt, still not entirely successful.
> Hmm, back to basics I think. Install the standard ivtv-0.8.x > (http://ivtvdriver.org/viewcvs/ivtv/branches/0.8.tar.gz?view=tar). > > 1) Load the driver and post the INIT IVTV messages (I removed nvidia, forcedeth and ACPI messages) ivtv: ==================== START INIT IVTV ==================== ivtv: version 0.8.1 (development snapshot compiled on Sat 18 Nov 2006 10:15:48 PM CET) loading ivtv: Linux version: 2.6.18-1.2849.fc6 SMP mod_unload 686 REGPARM 4KSTACKS gcc-4.1 ivtv: In case of problems please include the debug info between ivtv: the START INIT IVTV and END INIT IVTV lines, along with ivtv: any module options, when mailing the ivtv-users mailinglist. ivtv0: Autodetected Hauppauge card (cx23416 based) i2c_adapter i2c-0: nForce2 SMBus adapter at 0x5000 i2c_adapter i2c-1: nForce2 SMBus adapter at 0x5040 ivtv0: Unreasonably low latency timer, setting to 64 (was 32) ivtv0: loaded v4l-cx2341x-enc.fw firmware (262144 bytes) tveeprom 2-0050: Hauppauge model 26559, rev C260, serial# 7626017 tveeprom 2-0050: tuner model is LG S001D MK3 (idx 60, type 38) tveeprom 2-0050: TV standards PAL(B/G) PAL(I) SECAM(L/L') PAL(D/D1/K) (eeprom 0x74) tveeprom 2-0050: audio processor is CX25843 (idx 37) tveeprom 2-0050: decoder processor is CX25843 (idx 30) tveeprom 2-0050: has radio, has no IR remote ivtv0: Autodetected Hauppauge WinTV PVR-150 tuner 2-0043: chip found @ 0x86 (ivtv i2c driver #0) tda9887 2-0043: tda988[5/6/7] found @ 0x43 (tuner) tuner 2-0061: chip found @ 0xc2 (ivtv i2c driver #0) cx25840 2-0044: cx25843-23 found @ 0x88 (ivtv i2c driver #0) cx25840 2-0044: loaded v4l-cx25840.fw firmware (16382 bytes) wm8775 2-001b: chip found @ 0x36 (ivtv i2c driver #0) ivtv0: Encoder revision: 0x02050032 ivtv0: Registered device video0 for encoder MPEG ivtv0: Registered device video32 for encoder YUV ivtv0: Registered device vbi0 for encoder VBI ivtv0: Registered device video24 for encoder PCM audio ivtv0: Registered device radio0 for encoder radio tuner 2-0061: type set to 38 (Philips PAL/SECAM multi (FM1216ME MK3)) ivtv0: Initialized Hauppauge WinTV PVR-150, card #0 ivtv: ==================== END INIT IVTV ==================== > 2) run v4l2-ctl -i 1 > 3) start a capture and run in another shell v4l2-ctl --log-status. Post > the output. Status Log: ivtv0: ================= START STATUS CARD #0 ================= tveeprom 2-0050: Hauppauge model 26559, rev C260, serial# 7626017 tveeprom 2-0050: tuner model is LG S001D MK3 (idx 60, type 38) tveeprom 2-0050: TV standards PAL(B/G) PAL(I) SECAM(L/L') PAL(D/D1/K) (eeprom 0x74) tveeprom 2-0050: audio processor is CX25843 (idx 37) tveeprom 2-0050: decoder processor is CX25843 (idx 30) tveeprom 2-0050: has radio, has no IR remote tda9887 2-0043: Data bytes: b=0x14 c=0x6e e=0x49 tuner 2-0061: Tuner mode: analog TV tuner 2-0061: Frequency: 400.00 MHz tuner 2-0061: Standard: 0x0000000f cx25840 2-0044: Video signal: present cx25840 2-0044: Detected format: PAL-BDGHI cx25840 2-0044: Specified standard: PAL-BDGHI cx25840 2-0044: Specified video input: S-Video (Luma In1, Chroma In5) cx25840 2-0044: Specified audioclock freq: 48000 Hz cx25840 2-0044: Detected audio mode: forced mode cx25840 2-0044: Detected audio standard: no detected audio standard cx25840 2-0044: Audio muted: no cx25840 2-0044: Audio microcontroller: stopped cx25840 2-0044: Configured audio standard: automatic detection cx25840 2-0044: Configured audio system: automatic standard and mode detection cx25840 2-0044: Specified audio input: External cx25840 2-0044: Preferred audio mode: stereo cx25840 2-0044: Selected 65 MHz format: autodetect cx25840 2-0044: Selected 45 MHz format: chroma wm8775 2-001b: Input: 2 ivtv0: Stream: MPEG-2 Program Stream ivtv0: Video: 720x576, 25 fps ivtv0: Video: MPEG-2, 4x3, Variable Bitrate, 6000000, Peak 8000000 ivtv0: Video: GOP Size 12, 2 B-Frames, GOP Closure, No 3:2 Pulldown ivtv0: Audio: 48 kHz, Layer II, 224 kbps, Stereo, No Emphasis, No CRC ivtv0: Spatial Filter: Manual, Luma 1D Horizontal, Chroma 1D Horizontal, 0 ivtv0: Temporal Filter: Manual, 0 ivtv0: Median Filter: Off, Luma [0, 255], Chroma [0, 255] ivtv0: ================== END STATUS CARD #0 ================== > 4) run (while capture is still in progress) 'ivtvctl -R chip=cx2584x' > and post the output. > Still no registers: I ran the ivtvctl from ivtv-0.8.0-121.fc6.at, and to be sure I also tried the ivtvctl from the snapsjot I compiled yesterday, but with the same result. I did not install anything from the snapshot except ivtv.ko. tvr:~> ivtvctl -R chip=cx2584x 2>&1 | head -10 ioctl: VIDIOC_INT_G_REGISTER failed for 0x00000000 ioctl: VIDIOC_INT_G_REGISTER failed for 0x00000001 ioctl: VIDIOC_INT_G_REGISTER failed for 0x00000002 ioctl: VIDIOC_INT_G_REGISTER failed for 0x00000003 ioctl: VIDIOC_INT_G_REGISTER failed for 0x00000004 ioctl: VIDIOC_INT_G_REGISTER failed for 0x00000005 ioctl: VIDIOC_INT_G_REGISTER failed for 0x00000006 ioctl: VIDIOC_INT_G_REGISTER failed for 0x00000007 ioctl: VIDIOC_INT_G_REGISTER failed for 0x00000008 ioctl: VIDIOC_INT_G_REGISTER failed for 0x00000009 > Now go back to ivtv-0.3.2q and: > > 1) Load the driver and post the INIT IVTV messages Linux video capture interface: v1.00 ivtv: ==================== START INIT IVTV ==================== ivtv: version 0.3.2 (q) loading ivtv: Linux version: 2.6.11-1.27_FC3 686 REGPARM 4KSTACKS gcc-3.4 ivtv: In case of problems please include the debug info ivtv: between the START INIT IVTV and END INIT IVTV lines when ivtv: mailing the ivtv-devel mailinglist. ivtv: Autodetected WinTV PVR 150 card ivtv: Found an iTVC16 based chip ivtv: Unreasonably low latency timer, setting to 64 (was 32) ivtv: XXX PCI device: 0x01e0 vendor: 0x10de tveeprom: Hauppauge: model = 26559, rev = C260, serial# = 7626017 tveeprom: tuner = LG S001D MK3 (idx = 60, type = 58) tveeprom: tuner fmt = PAL(D/K) (eeprom = 0x74, v4l2 = 0x00400e17) tveeprom: audio_processor = MSP3410D (type = 5) ivtv: i2c attach [client=tveeprom[0],ok] ivtv: Tuner Type 58, Tuner formats 0x00400e17, Radio: yes, Model 0x008d2590, Revision 0x00000001 ivtv: Radio detected tuner: Ignoring new-style parameters in presence of obsolete ones tuner: chip found at addr 0xc2 i2c-bus ivtv i2c driver #0 ivtv: i2c attach [client=(tuner unset),ok] cx25840: FW image '/lib/modules/HcwMakoA.ROM' of size 14264 loaded. cx25840: FW image md5 digest: 3a4803384f749d644ee1f1ca9dcb12fa cx25840: FW image sha1 digest: 2b5e6292b7391c980b93d156cf6b34178ce770f6 ivtv: i2c attach [client=cx25840[0],ok] ivtv: i2c attach [client=wm8775[0],ok] ivtv: Encoder revision: 0x02050032 ivtv: Encoder Firmware may be buggy, use version 0x02040011 ivtv: Configuring WinTV PVR 150 card with 5 streams ivtv: Registered v4l2 device, streamtype 0 minor 0 ivtv: Create DMA stream 0 using 1024 16384 byte buffers 0 kbytes total ivtv: Allocate DMA stream 0 using 1024 16384 byte buffers 16777216 kbytes total ivtv: Registered v4l2 device, streamtype 1 minor 32 ivtv: Create DMA stream 1 ivtv: Allocate DMA stream 1 ivtv: Registered v4l2 device, streamtype 2 minor 224 ivtv: Create stream 2 using 40 52224 byte buffers 0 kbytes total ivtv: Allocate stream 2 using 40 52224 byte buffers 2097152 kbytes total ivtv: Registered v4l2 device, streamtype 3 minor 24 ivtv: Create DMA stream 3 using 455 4608 byte buffers 0 kbytes total ivtv: Allocate DMA stream 3 using 455 4608 byte buffers 2097152 kbytes total ivtv: Registered v4l2 device, streamtype 4 minor 64 ivtv: Create stream 4 ivtv: Allocate stream 4 ivtv: Setting Tuner 58 tuner: type set to 58 (LG PAL TAPE-S001D) by ivtv i2c driver #0 ivtv: Switching standard to PAL. ivtv: Initialized WinTV PVR 150, card #0 ivtv: ==================== END INIT IVTV ==================== ivtv: ivtv_enc_thread: pid = 1974, itv = 0xd0b09ea0 > 2) Select a working S-Video input (let me know which input you chose) ivtvctl -p 1 ioctl VIDIOC_S_INPUT ok Video input set to 1 > 3) Start a capture and run cx25840ctl -l and post the output. > Opening /dev/video0 SLEEP=0 (0x0) "Do not power down" DIGITAL_PWR_DN=0 (0x0) "Do not gate" REF_CLK_SEL=1 (0x1) "Differential signal required on crystal pins" PWR_DN_VID_PLL=0 (0x0) "Do not power down" PWR_DN_AUX_PLL=0 (0x0) "Do not power down" AUTO_INC_DIS=0 (0x0) "Do the auto-address increment" SLV_SI_DIS=0 (0x0) "Glitch filters and slew rate control enabled" FORCE_CHIP_SEL_VIPCLK=0 (0x0) "Use the CHIP_SEL/VIPCLK pin for 12C decode" PREFETCH_EN=0 (0x0) "Disable" PWR_DN_PLL_REG1=0 (0x0) "" PWR_DN_PLL_REG2=0 (0x0) "" DEVICE_ID=-1 (0xFFFFFFFF) "i2c receive failed for 0x101" SOFT_RST=0 (0x0) "Deassert reset" CH_SEL_ADC2=0 (0x0) "Analog input CH{2}" DUAL_MODE_ADC2=0 (0x0) "Normal mode" CHIP_ACFG_DIS=0 (0x0) "Allow VID_PLL_INT, VID_PLL_FRAC, and AFE control" CH_1__SOURCE=0 (0x0) "CVBS1/Y1" CH_2__SOURCE=1 (0x1) "CVBS5/C1/Pb2" CH_3__SOURCE=0 (0x0) "CVBS7/C3/Pr1" EN_12DB_CH1=0 (0x0) "Disable" EN_12DB_CH2=0 (0x0) "Disable" EN_12DB_CH3=0 (0x0) "Disable" HALF_BW_CH1=0 (0x0) "" HALF_BW_CH2=0 (0x0) "" HALF_BW_CH3=0 (0x0) "" VGA_SEL_CH1=0 (0x0) "Video decoder drives VGA gain setting" VGA_SEL_CH2=0 (0x0) "Video decoder drives VGA gain setting" VGA_SEL_CH3=0 (0x0) "Video decoder drives VGA gain setting" CLAMP_SEL_CH1=0 (0x0) "Video decoder drives clamp level" CLAMP_SEL_CH2=1 (0x1) "Clamp level is fixed at 3'b111 (midcode clamp). Use for" CLAMP_SEL_CH3=1 (0x1) "Clamp level is fixed at 3'b111 (midcode clamp). Use for" CHROMA_IN_SEL=1 (0x1) "ADC 2" LUMA_IN_SEL=0 (0x0) "ADC 1" AUD_IN_SEL=1 (0x1) "Miscellaneous Chip Control input" CLAMP_EN_CH1=1 (0x1) "Enable (power-up)" CLAMP_EN_CH2=0 (0x0) "Disable" CLAMP_EN_CH3=0 (0x0) "Disable" DROOP_COMP_CH1=1 (0x1) "" DROOP_COMP_CH2=0 (0x0) "" DROOP_COMP_CH3=0 (0x0) "" BYPASS_CH1=0 (0x0) "" BYPASS_CH2=0 (0x0) "" BYPASS_CH3=0 (0x0) "" IREF_SEL=0 (0x0) "" VID_PLL_INT=15 (0xF) "" VID_PLL_POST=4 (0x4) "" AUX_PLL_INT=10 (0xA) "" AUX_PLL_POST=24 (0x18) "" VID_PLL_FRAC1=254 (0xFE) "" VID_PLL_FRAC2=226 (0xE2) "" VID_PLL_FRAC3=43 (0x2B) "" VID_PLL_FRAC4=0 (0x0) "" AUX_PLL_FRAC1=229 (0xE5) "" AUX_PLL_FRAC2=214 (0xD6) "" AUX_PLL_FRAC3=152 (0x98) "" AUX_PLL_FRAC4=0 (0x0) "" GPIO0_OUT_EN=0 (0x0) "Disable" GPIO1_OUT_EN=0 (0x0) "Disable" CHIP_SEL_VIPCLK_OUT_EN=0 (0x0) "Disable" IRQN_OUT_EN=0 (0x0) "Disable" IR_RX_OUT_EN=0 (0x0) "Disable" IR_TX_OUT_EN=0 (0x0) "Disable" DVALID_OUT_EN=0 (0x0) "Disable" FIELD_OUT_EN=0 (0x0) "Disable" HRESET_OUT_EN=0 (0x0) "Disable" VRESET_OUT_EN=0 (0x0) "Disable" VID_OUT_EN=1 (0x1) "Enable" PIXCLK_OUT_EN=1 (0x1) "Enable" SA_SDIN_OUT_EN=0 (0x0) "Disable" SA_BCLKIN_OUT_EN=0 (0x0) "Disable" SA_WCLKIN_OUT_EN=0 (0x0) "Disable" SA_SDOUT_OUT_EN=1 (0x1) "Enable" SA_BCLKOUT_OUT_EN=1 (0x1) "Enable" SA_WCLKOUT_OUT_EN=1 (0x1) "Enable" PLL_CLK_OUT_EN=1 (0x1) "Enable" AC_OUT_OUT_EN=0 (0x0) "Disable" AC_IN_OUT_EN=0 (0x0) "Disable" IRQ_N_PRGM4=0 (0x0) "IRQ_N/PRGM4 is active low" VID_IRQ_STAT=0 (0x0) "Interrupt is not active" IR_IRQ_STAT=0 (0x0) "Interrupt is not active" VID_OUT_SPD=2 (0x2) "" VID_CTRL_SPD=0 (0x0) "Medium" AC_OUT_SPD=0 (0x0) "Medium" SA_OUT_SPD=0 (0x0) "Medium" GEN_OUT_SPD=0 (0x0) "Medium" GPIO0_OUT_SEL=0 (0x0) "GPO[0]" GPIO1_OUT_SEL=0 (0x0) "GPO[1]" CHIPSEL_OUT_SEL=0 (0x0) "GPO[0]" IRQN_OUT_SEL=0 (0x0) "IRQ_N/PRGM4" IR_RX_OUT_SEL=0 (0x0) "GPO[2]" IR_TX_OUT_SEL=0 (0x0) "IR_TX/PRGM6" DVALID_PRGM0_OUT_SEL=0 (0x0) "DVALID" FIELD_PRGM1_OUT_SEL=0 (0x0) "FIELD" HRESET_PRGM2_OUT_SEL=0 (0x0) "HRESET" VRESET_HCTL_PRGM3_OUT_SEL=0 (0x0) "VRESET/HCTL/PRGM3" VID_DATA_OUT_SEL=0 (0x0) "" PIXCLK_OUT_SEL=0 (0x0) "" AC_OUT_SEL=0 (0x0) "GPO[3]. AC_SYNC, AC_SDOUT" SA_OUT_OUT_SEL=0 (0x0) "SA_WCLK_OUT, SA_BCLK_OUT, GPO[2]" SA_IN_OUT_SEL=0 (0x0) "SA_WCLK_OUT, SA_BCLK_OUT, SA_SDOUT" AUX_PLL_AOUT_SEL=1 (0x1) "Auxiliary PLL" AUX_PLL_DOUT_SEL=0 (0x0) "PLL_CLK/PRGM7" AC_BITCLK_IN_SEL=0 (0x0) "" AC_SDIN_IN_SEL=1 (0x1) "DVALID/PRGM0" GPI0_IN_SEL=7 (0x7) "" GPI1_IN_SEL=8 (0x8) "HRESET/PRGM2" GPI2_IN_SEL=6 (0x6) "" GPI3_IN_SEL=11 (0xB) "" GPO_OUT=0 (0x0) "" GPI_IN=3 (0x3) "" SA_MCLK_DIV=16 (0x10) "" SA_MCLK_SEL=1 (0x1) "PLL_CLK/PRGM7 is divided by the alternate post-divider" VID_COUNT=1151992 (0x1193F8) "" EN_AV_LOCK=0 (0x0) "" AUD_LOCK_KD_SHIFT=2 (0x2) "" AUD_LOCK_KI_SHIFT=2 (0x2) "" AUD_COUNT=24575 (0x5FFF) "" AUD_LOCK_FREQ_SHIFT=2 (0x2) "" AUD_LOCK_KD_MULT=1 (0x1) "" AUD_LOCK_KI_MULT=1 (0x1) "" PWR_DN_TUNING=0 (0x0) "Do not power down filter tuning" PWR_DN_DLL1=0 (0x0) "Do not power down DLL1" PWR_DN_DLL2=0 (0x0) "Do not power down DLL2" PWR_DN_ADC1=0 (0x0) "Do not power down ADC1" PWR_DN_ADC2=0 (0x0) "Do not power down Miscellaneous Chip Control" PWR_DN_CH1=0 (0x0) "Do not power down Channel 1" PWR_DN_CH2=0 (0x0) "Do not power down Channel 2" PWR_DN_CH3=0 (0x0) "Do not power down Channel 3" SLEEP_ANALOG_MSK=0 (0x0) "SLEEP powers down analog subsystem" SLEEP_DLL_MSK=0 (0x0) "SLEEP powers down DLL (5x clock) circuitry" SLEEP_PLL_MSK=0 (0x0) "SLEEP powers down PLLs" VCLK_GATE_MSK=0 (0x0) "DIG_PWR_ON disables high-speed video clock (VCLK)" CLK5x_GATE_MSK=0 (0x0) "DIG_PWR_ON disables high-speed audio clock (CLK5x)" SCLK_GATE_MSK=0 (0x0) "DIG_PWR_ON disables sample clock (SCLK) and SA master" FOUR_X_CLK_ADC=0 (0x0) "5x output" VREG_D_1_0_=0 (0x0) "1.20 V" VREF_CTRL_ADC=0 (0x0) "1.60 V" BIAS_CTRL_ADC_1_0_=0 (0x0) "50 ��A" BIAS_CTRL_ADC_2_=0 (0x0) "1.6 V, 0.8 V" BIAS_CTRL_ADC_4_3_=3 (0x3) "" BIAS_CTRL_ADC_6_5_=0 (0x0) "50 ��A" S2DIFF_BIAS_1_0_=2 (0x2) "" FILTER_BIAS_1_0_=2 (0x2) "" TUNE_FIL_RST=0 (0x0) "" CH_SEL_ADC1=0 (0x0) "Connects ADC1 to output of filter." DISCONNECT_CH1=0 (0x0) "Enable filter" TEST_MODE_CH1=0 (0x0) "Do not connect" TUNE_IN_4_0_=0 (0x0) "" FORCE_TUNING=0 (0x0) "Do not override" TUNE_OUT=21 (0x15) "" TUNING_READY=1 (0x1) "Filter tuning complete" VID_DUAL_FLAG_POL=0 (0x0) "Noninverted polarity" AUD_DUAL_FLAG_POL=0 (0x0) "Noninverted polarity" PLL_SPMP=4 (0x4) "" VID_PLL_DDS=0 (0x0) "Enable" AUX_PLL_DDS=0 (0x0) "Enable" VID_PLL_RST=0 (0x0) "Do not reset" AUX_PLL_RST=0 (0x0) "Do not reset" AUX_PLL_LOCK=1 (0x1) "Locked" VID_PLL_LOCK=1 (0x1) "Locked" AUX_PLL_UNLOCK=0 (0x0) "No unlock detected" VID_PLL_UNLOCK=0 (0x0) "No unlock detected" DLL1_FLD=1 (0x1) "" DLL1_UP_OVRD=0 (0x0) "" DLL1_DOWN_OVRD=0 (0x0) "" DLL1_CHPREF=4 (0x4) "" DLL1_COMP_GT=4 (0x4) "" DLL1_COMP_LT=3 (0x3) "" DLL1_DEPTH=6 (0x6) "" DLL1_DLYS=1 (0x1) "" DLL1_CURRSET=8 (0x8) "" DLL1_BYPASS=0 (0x0) "" DLL2_Diagnostic_Control_1_REG=0 (0x0) "" DLL2_FLD=1 (0x1) "" DLL2_UP_OVRD=0 (0x0) "" DLL2_DOWN_OVRD=0 (0x0) "" DLL2_CHPREF=4 (0x4) "" DLL2_COMP_GT=4 (0x4) "" DLL2_COMP_LT=3 (0x3) "" DLL2_DEPTH=6 (0x6) "" DLL2_DLYS=1 (0x1) "" DLL2_CURRSET=3 (0x3) "" DLL2_BYPASS=0 (0x0) "" WIN=0 (0x0) "Next carrier edge predicted to be 16 RX clocks 3/+3" EDG=0 (0x0) "Disable" DMD=0 (0x0) "Disable receive carrier demodulation, receive data as simple logic" MOD=0 (0x0) "Disable transmit carrier modulation, transmit data as simple logic" RFE=0 (0x0) "Disable and reset receive FIFO to all 0s" TFE=0 (0x0) "Disable and reset transmit FIFO to all 0s" RXE=0 (0x0) "Disable receiver" TXE=0 (0x0) "Disable transmitter" RIC=0 (0x0) "Receive FIFO service interrupt/DMA request asserted when RX" TIC=0 (0x0) "Transmit FIFO service interrupt/DMA request asserted when TX" CPL=0 (0x0) "If mod/demodulation enabled, 1s are transmitted and received as" LBM=0 (0x0) "Transmit and receive operation functions normally through the IR" R=0 (0x0) "Load Rx FIFO with 1s and Rx_data_lh level on timer overflow;" TCD=65535 (0xFFFF) "" RCD=65535 (0xFFFF) "" CDC=0 (0x0) "1 TX clock high and 15 TX clocks low" RTO=0 (0x0) "Receive pulse width counter has not reached its limit" ROR=0 (0x0) "Receive FIFO contains one or more empty entries or is full but has" TBY=0 (0x0) "Receiver is idle" RSR=0 (0x0) "If RIC=0 in IR_CNTL_REG, receive FIFO is less than half full. If" TSR=1 (0x1) "IF TIC=0, transmit FIFO is half full or less." ROE=1 (0x1) "Receive FIFO overrun interrupt enabled" RSE=1 (0x1) "Receive FIFO interrupt enabled" TSE=1 (0x1) "Transmit FIFO/Idle interrupt enabled" LPF=0 (0x0) "" RX_TX_FIFO=0 (0x0) "" RX_TX_LVL=0 (0x0) "" RXNDV=0 (0x0) "No more data in the RX FIFO" VID_FMT_SEL=0 (0x0) "AUTO-DETECT" SQ_PIXEL=0 (0x0) "" ACFG_DIS=1 (0x1) "Disable" AFD_PAL_SEL=0 (0x0) "PAL-BDGHI" AFD_NTSC_SEL=0 (0x0) "NTSC-M" AFD_ACQUIRE=0 (0x0) "The auto-detect state machine operates normally." INPUT_MODE=1 (0x1) "Y/C" MAN_SC_FAST_LOCK=0 (0x0) "" AUTO_SC_LOCK=0 (0x0) "Manual mode. Lock speed is determined by" CKILLEN=1 (0x1) "Enable" CAGCEN=1 (0x1) "Enable" WCEN=1 (0x1) "" FAST_LOCK_MD=0 (0x0) "" CLR_LOCK_STAT=0 (0x0) "" COMB_NOTCH_MODE=1 (0x1) "Notch data is interpreted as chroma" CKILL_MODE=0 (0x0) "Chroma output is forced to 0, and luma output is generated" AFD_PALM_SEL=0 (0x0) "NTSC will be detected according to the AFD_NTSC_SEL bit." AFD_FORCE_PAL=0 (0x0) "The auto-detect algorithm proceeds normally." AFD_FORCE_PALNC=0 (0x0) "The auto-detect algorithm proceeds normally." AFD_FORCE_SECAM=0 (0x0) "The auto-detect algorithm proceeds normally." AFD_PAL60_DIS=0 (0x0) "PAL-60 can be detected and discriminate from NTSC-4.43" OUT_MODE=2 (0x2) "" MODE10B=1 (0x1) "Luma and Chroma Output have 10 bits of resolution" VBIHACTRAW_EN=1 (0x1) "Enable" ANC_DATA_EN=1 (0x1) "Enable" TASKBIT_VAL=1 (0x1) "" BLUE_FIELD_ACT=0 (0x0) "" BLUE_FIELD_EN=0 (0x0) "Disable" CLAMPRAW_EN=1 (0x1) "Enable" SWAPRAW=0 (0x0) "Even samples on chroma; odd samples on luma" ACTFMT=1 (0x1) "Active is horizontal active" VALIDFMT=0 (0x0) "Valid indicates nonscaled pixels" HSFMT=0 (0x0) "Nominal width" CLK_INVERT=1 (0x1) "" CLK_GATING=0 (0x0) "" DCMODE=0 (0x0) "Data Count is number of blocks of 4 UDWs, with padding" IDID0_SOURCE=0 (0x0) "IDID0 register" VIP_OPT_AL=0 (0x0) "VBLANK" VIPBLANK_EN=0 (0x0) "Disable" VIPCLAMP_EN=1 (0x1) "Enable" POLAR=0 (0x0) "" IDID0_9_2__LOW=0 (0x0) "" IDID1_9_2__LOW=128 (0x80) "" IDID0_1_0__HIGH=0 (0x0) "" IDID1_1_0__HIGH=0 (0x0) "" EN_A=0 (0x0) "" EN_B=0 (0x0) "" EN_C=0 (0x0) "" AUD_ANC_EN=0 (0x0) "Disable" SAMPLE_RATE=0 (0x0) "48 kHz" AUD_GRP=0 (0x0) "Audio Group1" MV_CDAT=0 (0x0) "" MV_PSP=0 (0x0) "" MV_CS=0 (0x0) "" MV_T3CS=0 (0x0) "" MV_TYPE2_PAIR=0 (0x0) "" AFD_FMT_STAT=-1 (0xFFFFFFFF) "i2c receive failed for 0x40d" FIELD=-1 (0xFFFFFFFF) "i2c receive failed for 0x40d" SRC_FIFO_OFLOW=-1 (0xFFFFFFFF) "i2c receive failed for 0x40d" SRC_FIFO_UFLOW=-1 (0xFFFFFFFF) "i2c receive failed for 0x40d" VSYNC=-1 (0xFFFFFFFF) "i2c receive failed for 0x40d" HLOCK=1 (0x1) "" SRC_LOCK=0 (0x0) "" VLOCK=1 (0x1) "" CSC_LOCK=1 (0x1) "" AGC_LOCK=1 (0x1) "" VPRES=1 (0x1) "" SPECIAL_PLAY_N=1 (0x1) "" SRC_FIFO_OFLOW_STAT=-1 (0xFFFFFFFF) "i2c receive failed for 0x410" SRC_FIFO_UFLOW_STAT=-1 (0xFFFFFFFF) "i2c receive failed for 0x410" CSC_LOCK_CHANGE_STAT=-1 (0xFFFFFFFF) "i2c receive failed for 0x410" VLOCK_CHANGE_STAT=-1 (0xFFFFFFFF) "i2c receive failed for 0x410" HLOCK_CHANGE_STAT=-1 (0xFFFFFFFF) "i2c receive failed for 0x410" VSYNC_TRAIL_STAT=-1 (0xFFFFFFFF) "i2c receive failed for 0x410" FMT_CHANGE_STAT=-1 (0xFFFFFFFF) "i2c receive failed for 0x410" END_VBI_ODD_STAT=-1 (0xFFFFFFFF) "i2c receive failed for 0x410" END_VBI_EVEN_STAT=1 (0x1) "" MV_CHANGE_STAT=0 (0x0) "" VPRES_CHANGE_STAT=1 (0x1) "" CC_DAT_AVAIL_STAT=0 (0x0) "" GS1_DAT_AVAIL_STAT=0 (0x0) "" GS2_DAT_AVAIL_STAT=0 (0x0) "" WSS_DAT_AVAIL_STAT=0 (0x0) "" SRC_FIFO_OFLOW_MSK=1 (0x1) "" SRC_FIFO_UFLOW_MSK=1 (0x1) "" CSC_LOCK_CHANGE_MSK=1 (0x1) "" VLOCK_CHANGE_MSK=1 (0x1) "" HLOCK_CHANGE_MSK=1 (0x1) "" VSYNC_TRAIL_MSK=1 (0x1) "" FMT_CHANGE_MSK=1 (0x1) "" END_VBI_ODD_MSK=1 (0x1) "" END_VBI_EVEN_MSK=1 (0x1) "" MV_CHANGE_MSK=1 (0x1) "" VPRES_CHANGE_MSK=1 (0x1) "" CC_DAT_AVAIL_MSK=1 (0x1) "" GS1_DAT_AVAIL_MSK=1 (0x1) "" GS2_DAT_AVAIL_MSK=1 (0x1) "" WSS_DAT_AVAIL_MSK=1 (0x1) "" BRIGHT=255 (0xFF) "" CNTRST=126 (0x7E) "" PEAK_SEL=0 (0x0) "+2.0 dB response @ center freq" PEAK_EN=0 (0x0) "Disable" RANGE=0 (0x0) "Range: 641016 Nominal 656 range with excursions" LUMA_CORE_SEL=0 (0x0) "No coring" HSCALE=0 (0x0) "" HFILT=0 (0x0) "Auto Mode" VSCALE=0 (0x0) "" VFILT=0 (0x0) "2-tap interpolation (available at all resolutions)" VS_INTRLACE=1 (0x1) "Interlace VS" LINE_AVG_DIS=0 (0x0) "PAL line averaging is enabled. Adjacent lines are averaged" USAT=126 (0x7E) "" VSAT=126 (0x7E) "" HUE=0 (0x0) "" C_CORE_SEL=0 (0x0) "No coring" CHR_DELAY=0 (0x0) "0" VBI_MD_LINE1=0 (0x0) "No VBI data slicing" VBI_MD_LINE2=0 (0x0) "" VBI_MD_LINE3=0 (0x0) "" VBI_MD_LINE4=0 (0x0) "" VBI_MD_LINE5=0 (0x0) "" VBI_MD_LINE6=0 (0x0) "" VBI_MD_LINE7=0 (0x0) "" VBI_MD_LINE8=0 (0x0) "" VBI_MD_LINE9=0 (0x0) "" VBI_MD_LINE10=0 (0x0) "" VBI_MD_LINE11=0 (0x0) "" VBI_MD_LINE12=0 (0x0) "" VBI_MD_LINE13=0 (0x0) "" VBI_MD_LINE14=0 (0x0) "" VBI_MD_LINE15=0 (0x0) "" VBI_MD_LINE16=0 (0x0) "" VBI_MD_LINE17=0 (0x0) "" FC_SEARCH_MODE=0 (0x0) "Frame code match is declared only if frame code (start code," FC_ALT1_TYPE=0 (0x0) "" FC_ALT2_TYPE=0 (0x0) "" FC_ALT1=0 (0x0) "" FC_ALT2=0 (0x0) "" ADAPT_SLICE_DIS=0 (0x0) "Slice level comes from averaging points in the clock run-in." EDGE_RESYNC_EN=1 (0x1) "Sample point timing is resynchronized upon detecting any" CRI_MARG_SCALE=1 (0x1) "Use default timing margin" VPS_DEC_DIS=0 (0x0) "VPS formats are decoded based on a two-bit biphase pattern." MOJI_PACK_DIS=0 (0x0) "WST525, system D formats cause the decoder to extract the" TTX_PKTADRL_LB=0 (0x0) "" TTX_PKTADRL_HN=0 (0x0) "" TTX_PKTADRU_LN=15 (0xF) "" TTX_PKTADRU_HB=255 (0xFF) "" VBI1_SDID=9 (0x9) "" VBI2_SDID=10 (0xA) "" VBI3_SDID=11 (0xB) "" CC_FIFO_RST=0 (0x0) "" GS1_FIFO_RST=0 (0x0) "" GS2_FIFO_RST=0 (0x0) "" WSS_FIFO_RST=0 (0x0) "" HAMMING_TYPE=0 (0x0) "" CC_STAT=0 (0x0) "" CC_FIFO_DAT=0 (0x0) "" GS1_STAT=0 (0x0) "" GS1_FIFO_DAT=0 (0x0) "" GS2_STAT=0 (0x0) "" GS2_FIFO_DAT=0 (0x0) "" WSS_STAT=0 (0x0) "" WSS_FIFO_DAT=0 (0x0) "" VBI1_HDELAY=112 (0x70) "" VBI1_BITINC=153 (0x99) "" VBI1_SLICE_DIST=1 (0x1) "" VBI1_CRWIN=44 (0x2C) "" VBI1_FRAME_CODE=1 (0x1) "" VBI1_FC_LENGTH=3 (0x3) "" VBI1_CRI_TIME=13 (0xD) "" VBI1_CRI_MARGIN=4 (0x4) "" VBI1_CRI_LENGTH=12 (0xC) "" VBI1_PAYLD_LENGTH=8 (0x8) "" VBI1_FORMAT_TYPE=6 (0x6) "" VBI1_FIFO_MODE=2 (0x2) "" VBI1_HAM_EN=0 (0x0) "" VBI2_HDELAY=119 (0x77) "" VBI2_BITINC=136 (0x88) "" VBI2_SLICE_DIST=0 (0x0) "" VBI1_CRIWIN=84 (0x54) "" VBI2_FRAME_CODE=0 (0x0) "" VBI2_FC_LENGTH=0 (0x0) "" VBI2_CRI_TIME=2 (0x2) "" VBI2_CRI_MARGIN=4 (0x4) "" VBI2_CRI_LENGTH=1 (0x1) "" VBI2_PAYLD_LENGTH=10 (0xA) "" VBI2_FORMAT_TYPE=4 (0x4) "" VBI2_FIFO_MODE=3 (0x3) "" VBI2_HAM_EN=0 (0x0) "" VBI3_HDELAY=110 (0x6E) "" VBI3_BITINC=1738 (0x6CA) "" VBI3_SLICE_DIST=3 (0x3) "" VBI3_CRWIN=6 (0x6) "" VBI3_FRAME_CODE=231 (0xE7) "" VBI3_FC_LENGTH=8 (0x8) "" VBI3_CRI_TIME=32 (0x20) "" VBI3_CRI_MARGIN=6 (0x6) "" VBI3_CRI_LENGTH=15 (0xF) "" VBI3_PAYLD_LENGTH=132 (0x84) "" VBI3_FORMAT_TYPE=2 (0x2) "" VBI3_FIFO_MODE=0 (0x0) "Do not load to payload FIFO" VBI3_HAM_EN=0 (0x0) "" HBLANK_CNT=-1 (0xFFFFFFFF) "i2c receive failed for 0x470" HACTIVE_CNT=720 (0x2D0) "" BGDEL_CNT=93 (0x5D) "" VBLANK_CNT=34 (0x22) "" VACTIVE_CNT=576 (0x240) "" V656BLANK_CNT=38 (0x26) "" SRC_DECIM_RATIO=543 (0x21F) "" UV_LPF_SEL=-1 (0xFFFFFFFF) "i2c receive failed for 0x47a" LUMA_LPF_SEL=-1 (0xFFFFFFFF) "i2c receive failed for 0x47a" LCOMB_2LN_EN=0 (0x0) "Disable" LCOMB_3LN_EN=0 (0x0) "Disable" CCOMB_2LN_EN=1 (0x1) "Enable" CCOMB_3LN_EN=0 (0x0) "Disable" SC_STEP=-1 (0xFFFFFFFF) "i2c receive failed for 0x47d" VBI_OFFSET=1 (0x1) "" FIELD_COUNT=-1 (0xFFFFFFFF) "i2c receive failed for 0x480" TEMPDEC=0 (0x0) "" TDFIELD=0 (0x0) "" TDALGN=0 (0x0) "Start on odd field" HR32=0 (0x0) "HRESET is 64 clocks wide" VPRES_VERT_EN=0 (0x0) "VPRES reflects the horizontal locking only." VT_LINE_CNT_HYST=0 (0x0) "2 consecutive fields with approximately 525/2 or 625/2" DEBOUNCE_COUNT=1 (0x1) "4 consecutive fields of stability" VGA_GAIN=32 (0x20) "" AGC_GAIN=1183 (0x49F) "" CLAMP_LEVEL=0 (0x0) "" VBI_GATE_EN=1 (0x1) "" VGA_AUTO_EN=1 (0x1) "Auto mode" VGA_CRUSH_EN=1 (0x1) "" AGC_AUTO_EN=1 (0x1) "Auto mode" CLAMP_AUTO_EN=1 (0x1) "Enable" VGA_SYNC=220 (0xDC) "" VGA_TRACK_RANGE=64 (0x40) "" VGA_ACQUIRE_RANGE=16 (0x10) "" DCC_LOOP_GAIN=2 (0x2) "" AGC_LOOP_GAIN=2 (0x2) "" SYNC_LOOP_GAIN=2 (0x2) "" BP_LOOP_GAIN=2 (0x2) "" DFT_THRESHOLD=63 (0x3F) "" BP_PERCENT=205 (0xCD) "" PLL_MAX_OFFSET=768 (0x300) "" PLL_KI=31 (0x1F) "" PLL_KD=22 (0x16) "" HTL_KI=2 (0x2) "" HTL_KD=2 (0x2) "" LCOMB_ERR_LIMIT=20 (0x14) "" LUMA_THRESHOLD=0 (0x0) "" CCOMB_ERR_LIMIT=80 (0x50) "" COMB_PHASE_LIMIT=20 (0x14) "" SYNC_TIP_INC=15 (0xF) "" SYNC_TIP_REDUCE=1 (0x1) "" MAJ_SEL=3 (0x3) "" MAJ_SEL_EN=0 (0x0) "Disable" CRUSH_FREQ=0 (0x0) "Field rate" WTW_EN=0 (0x0) "100 IRE peak threshold" DFE_RST_MSK=0 (0x0) "" SRC_RST_MSK=0 (0x0) "" YCSEP_RST_MSK=0 (0x0) "" VTG_RST_MSK=0 (0x0) "" LUMA_RST_MSK=0 (0x0) "" CHROMA_RST_MSK=0 (0x0) "" SCALE_RST_MSK=0 (0x0) "" VBI_RST_MSK=0 (0x0) "" MVDET_RST_MSK=0 (0x0) "" VOF_RST_MSK=0 (0x0) "" REG_RST_MSK=0 (0x0) "" VD_SOFT_RST=0 (0x0) "" REV_ID=3 (0x3) "" APL_DETECT_ENA=1 (0x1) "Forces the Y/C separation algorithm into notch mode" DL_ADDR_LB=0 (0x0) "" DL_ADDR_HB=0 (0x0) "" DL_DATA_CTL=0 (0x0) "" DL_MAP=3 (0x3) "" DL_AUTO_INC=0 (0x0) "Auto increment address on write" DL_ENABLE=0 (0x0) "Disable" START_MICROCNTL=0 (0x0) "" MOD_DET_STATUS0=0 (0x0) "" MOD_DET_STATUS1=-1 (0xFFFFFFFF) "i2c receive failed for 0x805" AUD_MODE_AUD_SYSTEM=15 (0xF) "" AUD_STANDARD=15 (0xF) "" PREF_MODE=4 (0x4) "" MUTE_NO_PREF_MODE=0 (0x0) "" DE_EMPHASIS_TIME=0 (0x0) "" FM_DEVIATION=0 (0x0) "Normal FM" MICROCNTL_VIDEO_FORMAT=4 (0x4) "" VIDEO_PRESENT=1 (0x1) "" FORMAT_45MHZ=0 (0x0) "Chroma" FORMAT_65MHZ=0 (0x0) "System DK" TUNER_OUTPUT_FORMAT=0 (0x0) "2nd IF" SOFT_RESET=0 (0x0) "" AC97_INT_DIS=1 (0x1) "Disable" AMC_INT_DIS=1 (0x1) "Disable" FC_INT_DIS=1 (0x1) "Disable" FDL_INT_DIS=1 (0x1) "Disable" IFL_INT_DIS=1 (0x1) "Disable" NLL_INT_DIS=1 (0x1) "Disable" NBER_INT_DIS=1 (0x1) "Disable" RDS_INT_DIS=1 (0x1) "Disable" AC97_INT=-1 (0xFFFFFFFF) "i2c receive failed for 0x813" AMC_INT=-1 (0xFFFFFFFF) "i2c receive failed for 0x813" AFC_INT=-1 (0xFFFFFFFF) "i2c receive failed for 0x813" FDL_INT=-1 (0xFFFFFFFF) "i2c receive failed for 0x813" IFL_INT=0 (0x0) "" NLL_INT=-1 (0xFFFFFFFF) "i2c receive failed for 0x813" NBER_INT=-1 (0xFFFFFFFF) "i2c receive failed for 0x813" RDS_INT=-1 (0xFFFFFFFF) "i2c receive failed for 0x813" AAGC_HYST1=5 (0x5) "" AAGC_HYST2=9 (0x9) "" AAGC_TH=14 (0xE) "" AAGC_GAIN_EN=0 (0x0) "Disable" AAGC_DEFAULT=32 (0x20) "" AAGC_DEFAULT_EN=0 (0x0) "Disable" AFE_12DB_EN=0 (0x0) "Disable" IF_SRC_MODE=0 (0x0) "TV audio input" PHASE_FIX=9 (0x9) "" PH_CH_SEL=0 (0x0) "Channel 1" PH_DBX_SEL=0 (0x0) "" DEMATRIX_MODE=0 (0x0) "" DMTRX_BYPASS=0 (0x0) "System decide dematrix mode" DEMATRIX_SEL_CTL=66 (0x42) "" SA_IN_SHIFT=0 (0x0) "" AC97_IN_SHIFT=0 (0x0) "" PATH1_SEL_CTL=2 (0x2) "" PATH1_AVC_RMS_CON=1 (0x1) "" PATH1_AVC_CR=0 (0x0) "2:1" PATH1_AVC_STEREO=0 (0x0) "" PATH1_AVC_AT=1 (0x1) "10 ms" PATH1_AVC_RT=1 (0x1) "10 ms" PATH1_AVC_CG=0 (0x0) "1" SOFT1_MUTE_EN=1 (0x1) "Enable" SRC1_MUTE_EN=0 (0x0) "Disable" SA_MUTE_EN=0 (0x0) "Disable" PAR_MUTE_EN=0 (0x0) "Disable" AC97_MUTE_EN=0 (0x0) "Disable" PATH1_VOLUME=36 (0x24) "" PATH1_BAL_LEVEL=0 (0x0) "" PATH1_BAL_LEFT=0 (0x0) "" PATH1_AVC_THRESH=32767 (0x7FFF) "" PATH1_EQ_BAND_SEL=0 (0x0) "500 Hz, 1 kHz, 2 kHz" PATH1_EQ_BASS_VOL=24 (0x18) "" PATH1_EQ_MID_VOL=24 (0x18) "" PATH1_EQ_TREBLE_VOL=24 (0x18) "" PATH1_SC_RMS_CON=3 (0x3) "" PATH1_SC_CR=2 (0x2) "" PATH1_SC_STEREO=1 (0x1) "Stereo Mode" PATH1_SC_AT=3 (0x3) "" PATH1_SC_RT=3 (0x3) "" PATH1_SC_THRESH=32767 (0x7FFF) "" PATH2_SEL_CTL=0 (0x0) "" PATH2_AVC_RMS_CON=7 (0x7) "" PATH2_AVC_CR=0 (0x0) "2:1" PATH2_AVC_STEREO=1 (0x1) "Stereo Mode" PATH2_AVC_AT=3 (0x3) "" PATH2_AVC_RT=6 (0x6) "" PATH2_AVC_CG=0 (0x0) "1" SOFT2_MUTE_EN=1 (0x1) "" SRC2_MUTE_EN=0 (0x0) "" PATH2_VOLUME=36 (0x24) "" PATH2_BAL_LEVEL=0 (0x0) "" PATH2_BAL_LEFT=0 (0x0) "" PATH2_AVC_THRESH=32767 (0x7FFF) "" PATH2_EQ_BAND_SEL=0 (0x0) "500 Hz, 1 kHz, 2 kHz" PATH2_EQ_BASS_VOL=24 (0x18) "" PATH2_EQ_MID_VOL=24 (0x18) "" PATH2_EQ_TREBLE_VOL=24 (0x18) "" PATH2_SC_RMS_CON=3 (0x3) "" PATH2_SC_CR=2 (0x2) "" PATH2_SC_STEREO=1 (0x1) "Stereo Mode" PATH2_SC_AT=3 (0x3) "" PATH2_SC_RT=3 (0x3) "" PATH2_SC_THRESH=32767 (0x7FFF) "" Sample_Rate_Converter_Status1_REG=10 (0xA) "" Sample_Rate_Converter_Status2_REG=2 (0x2) "" SRC1_PHASE_INC=99964 (0x1867C) "" SRC2_PHASE_INC=99964 (0x1867C) "" SRC3_PHASE_INC=87381 (0x15555) "" SRC3_FIFO_RD_TH=8 (0x8) "" SRC4_PHASE_INC=87381 (0x15555) "" SRC4_FIFO_RD_TH=8 (0x8) "" SRC5_PHASE_INC=66643 (0x10453) "" SRC5_FIFO_RD_TH=8 (0x8) "" SRC6_PHASE_INC=87381 (0x15555) "" SRC6_FIFO_RD_TH=8 (0x8) "" PARALLEL1_SRC_SEL=1 (0x1) "Select from SRC 4" PARALLEL2_SRC_SEL=2 (0x2) "" SERIAL_AUDIO_SRC_SEL=0 (0x0) "Select from SRC 3" AC97_SRC_SEL=3 (0x3) "" BASEBAND_BYPASS_CTL=0 (0x0) "Normal operation" SRC3_CLK_SEL=0 (0x0) "Select from serial audio WS" SRC3_IN_SEL=0 (0x0) "Select from path 1 output" SRC4_CLK_SEL=3 (0x3) "" SRC4_IN_SEL=2 (0x2) "" SRC5_CLK_SEL=2 (0x2) "" SRC5_IN_SEL=0 (0x0) "Select from analog demod outa, outc" SRC6_CLK_SEL=1 (0x1) "Select from AC97 RD (48 kHz)" SRC6_IN_SEL=0 (0x0) "Select from path 1 output" SA_IN_BCN_DEL=0 (0x0) "" SA_IN_WS_SEL=1 (0x1) "Left sample on SA_WCLK = 1" SA_IN_RIGHT_JUST=0 (0x0) "" SA_IN_SONY_MODE=1 (0x1) "Sony mode: 1st SA_BCLK_IN rising edge after" SA_IN_MASTER_MODE=0 (0x0) "" SA_UP2X_BYPASS=0 (0x0) "" SA_OUT_BCNT_DEL=0 (0x0) "" SA_OUT_WS_SEL=1 (0x1) "Left sample on SA_WCLK = 1" SA_OUT_RIGHT_JUST=0 (0x0) "" SA_OUT_SONY_MODE=1 (0x1) "Sony mode: 1st SA_BCLK_OUT rising edge after" SA_OUT_MASTER_MODE=1 (0x1) "Master: SA_BCLK_OUT, and SA_WCLK_OUT are" AC97_SHUTDOWN=0 (0x0) "" AC97_WAKE_UP_SYNC=0 (0x0) "" AC97_RST_ACL=0 (0x0) "" AC97_UP2X_BYPASS=0 (0x0) "" ACLMSTR_BIT1=0 (0x0) "AC_LINK interface disabled" ACLMSTR_4TO2_3_2_=0 (0x0) "Disable" ACLMSTR_4TO2_4_=0 (0x0) "Disable" ACLMSTR_12TO8_8__=0 (0x0) "Disable" ACLMSTR_12TO8_9_=0 (0x0) "Disable" ACLMSTR_12TO8_10_=0 (0x0) "Disable" ACLMSTR_12TO8_11_=0 (0x0) "" ACLMSTR_12TO8_12_=0 (0x0) "" ACLMSTR_16TO14_14_=0 (0x0) "" ACLMSTR_16TO14_15_=0 (0x0) "" ACLMSTR_16TO14_16_=0 (0x0) "" ACLCTRL00=0 (0x0) "" ACLCTRL01_1_0_=0 (0x0) "Disable" ACLCTRL02_1_0_=0 (0x0) "Disable" ACLCTRL03_1_0_=0 (0x0) "Disable" ACLCTRL04_1_0_=0 (0x0) "Disable" ACLCTRL05_5_0_=0 (0x0) "" ACLCTRL06_1_0_=0 (0x0) "Disable" ACLCTRL06_7_2_=0 (0x0) "" ACLCTRL07_1_0_=0 (0x0) "Disable" ACLCTRL07_7_2_=0 (0x0) "" ACLCTRL08_1_0_=0 (0x0) "Disable" ACLCTRL08_7_2_=0 (0x0) "" ACLCMD_15_0_=0 (0x0) "" ACLCMD_23_16_=0 (0x0) "" ACLGPOUT_15_0_=0 (0x0) "" ACLGPIN_15_0_=0 (0x0) "" ACLSTAT0_15_0_=0 (0x0) "" ACLSTAT0_23_16_=0 (0x0) "" LOWPOWER_0_=0 (0x0) "" LOWPOWER_7_1_=0 (0x0) "" LOWPOWER_20_8_=0 (0x0) "" ACL_TAG=0 (0x0) "" ACL_LINK_UPDATE=0 (0x0) "" RDS_I=44 (0x2C) "" Closing /dev/video0 > Well, that should give me all the info I need. I really don't understand > it. > Neither do I <g>. Han Holl
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