I have a diamond pvr550/yuan pg600 which seems to be closely related to
the pvr-150. In fact, after realizing that the tuner input was input 1,
not input 6, I was able to acquire a fairly good picture from 0.3.2a.
However this has not been the case since. I have even fiddled with the
code in the attempt to make "my" input 1 correspond with "other's" input
6, to no avail.
Ulf mentions in the readme that he has had to poke some bits at 0x43 on
the i2c-bus (which my card will report is the tda9887 chip, when probed)
and he is not entirely confident as to why. I removed that WI2C, but
have had no luck with the change. Is there any more 'black magic' that I
can fiddle with that occurs in 0.3.2b+? Or is the best bet to dig
through the code and discover which bit-pokings are different?
Thanks,
Jeff
On Mon, 2005-01-31 at 20:04 -0500, John Eckhart wrote:
> Hi all,
>
> I have been playing around with the settings for the pvr-150 NTSC and
> have mangaged to get the audio working fairly consistently. Per the
> spec-sheet, I removed some of the settings in Ulf's patch that the
> cx25840 should be able to automatically configure, and I also removed
> some settings where the register was getting set to it's default value
> during a reset (ie, redundant register sets).
>
> On my PVR-150 the audio works, and the video seems cleaner. I have a
> retail NTSC model (tuner=50). Can I get some feedback to see if this
> helps everyone else out there too?
>
> lspci -vv:
> 0000:01:0c.0 Multimedia video controller: Internext Compression Inc
> iTVC16 (CX23416) MPEG-2 Encoder (rev 01)
> Subsystem: Hauppauge computer works Inc.: Unknown device 8003
> Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop-
> ParErr- Stepping- SERR+ FastB2B-
> Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium
> >TAbort- <TAbort- <MAbort- >SERR- <PERR-
> Latency: 64 (32000ns min, 2000ns max), cache line size 08
> Interrupt: pin A routed to IRQ 10
> Region 0: Memory at e0000000 (32-bit, prefetchable)
> Capabilities: [44] Power Management version 2
> Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
> PME(D0-,D1-,D2-,D3hot-,D3cold-)
> Status: D0 PME-Enable- DSel=0 DScale=0 PME-
>
> modprobe tveeprom && dmesg | grep tveeprom:
> tveeprom: Hauppauge: model = 26052, rev = C185, serial# = 7578050
> tveeprom: tuner = TCL 2002N 6A (idx = 85, type = 50)
> tveeprom: tuner fmt = NTSC(M) (eeprom = 0x08, v4l2 = 0x00001000)
> tveeprom: audio_processor = MSP3410D (type = 5)
>
>
> ps. I don't have a PVR-500, but from what I can tell, this patch
> should work well for it as well.
>
> Let me know if it helps anyone. I'm also working on a patch that
> speeds up the firmware loading by an order of magnitude (ie. the
> driver starts in a second, instead of 10 seconds).
>
> Here is the patch:
>
> --- ivtv-0.3.2c.orig/driver/cx25840-driver.c 2005-01-06 14:05:01.000000000
> +0000
> +++ ivtv-0.3.2c/driver/cx25840-driver.c 2005-02-01 00:57:28.163515320
> +0000
> @@ -547,8 +547,8 @@
> CX25840_SET_DLL1_CURRSET(0x0008),
> // '*' (Default 0x0000) Reg: 0x015b Start bit: 1 Bit length: 4
> CX25840_SET_DLL2_COMP_LT(0x0003), //
> '*' (Default 0x0009) Reg: 0x015e Start bit: 1 Bit length: 3
> CX25840_SET_DLL2_CURRSET(0x0003), //
> '*' (Default 0x0000) Reg: 0x015f Start bit: 1 Bit length: 4
> - CX25840_SET_ACFG_DIS(0x0001), //
> 'Disable' (Default 0x0000) Reg: 0x0400 Start bit: 5 Bit length: 1
> - CX25840_SET_AUTO_SC_LOCK(0x0000), //
> 'Manual mode. Lock speed is determined by' (Default 0x0001) Reg:
> 0x0401 Start bit: 4 Bit length: 1
> + CX25840_SET_ACFG_DIS(0x0000), //
> 'Disable' (Default 0x0000) Reg: 0x0400 Start bit: 5 Bit length: 1
> + CX25840_SET_AUTO_SC_LOCK(0x0001), //
> 'Manual mode. Lock speed is determined by' (Default 0x0001) Reg:
> 0x0401 Start bit: 4 Bit length: 1
> CX25840_SET_COMB_NOTCH_MODE(0x0001), //
> 'Notch data is interpreted as chroma' (Default 0x000a) Reg: 0x0402
> Start bit: 2 Bit length: 2
> CX25840_SET_OUT_MODE(0x0002), //
> '*' (Default 0x0001) Reg: 0x0404 Start bit: 0 Bit length: 2
> CX25840_SET_MODE10B(0x0001), //
> 'Luma and Chroma Output have 10 bits of resolution' (Default 0x0000)
> Reg: 0x0404 Start bit: 2 Bit length: 1
> @@ -571,7 +571,7 @@
> CX25840_SET_SC_STEP(0x0a8263), //
> '*' (Default 0x001f) Reg: 0x047c Start bit: 0 Bit length: 8
> CX25840_SET_VBI_OFFSET(0x0001), //
> '*' (Default 0x0000) Reg: 0x047f Start bit: 0 Bit length: 5
> CX25840_SET_COMB_PHASE_LIMIT(0x0014), //
> '*' (Default 0x0020) Reg: 0x049f Start bit: 0 Bit length: 8
> - CX25840_SET_AUD_MODE_AUD_SYSTEM(0x0006), //
> '*' (Default 0x0000) Reg: 0x0808 Start bit: 0 Bit length: 4
> + CX25840_SET_AUD_MODE_AUD_SYSTEM(0x000f), //
> '*' (Default 0x0000) Reg: 0x0808 Start bit: 0 Bit length: 4
> CX25840_SET_AUD_STANDARD(0x000f), //
> '*' (Default 0x0000) Reg: 0x0808 Start bit: 4 Bit length: 4
> CX25840_SET_PREF_MODE(0x0004), //
> '*' (Default 0x0000) Reg: 0x0809 Start bit: 0 Bit length: 4
> CX25840_SET_PATH1_AVC_RMS_CON(0x0007), //
> '*' (Default 0x0049) Reg: 0x08d0 Start bit: 4 Bit length: 4
> @@ -1041,114 +1041,46 @@
> setting_sequencer(client, seq);
> break;
> }
> - case 7: {
> + case 7:
> + case 6: {
> u8 seq[]={
> - CX25840_TAG('T','u','n','n','e','r',' ','5','0','0'),
> -
> + CX25840_TAG('T','u','n','e','r','
> ',state->input==6?'1':'5',state->input==6?'5':'0','0'),
> +
> CX25840_SET_START_MICROCNTL(0x0000), // FW stop.
> - CX25840_SET_SOFT_RESET(0x0001), // Soft reset assert.
> - CX25840_SET_VD_SOFT_RST(0x0001), // Video assert
> + CX25840_SET_VD_SOFT_RST(0x0001), // Assert video reset
> + CX25840_SET_SOFT_RESET(0x0001), // Assert soft reset
> CX25840_EXECUTE,
>
> CX25840_SET_CH_SEL_ADC2(0x0001),
> - CX25840_SET_DUAL_MODE_ADC2(0x0000),
> - CX25840_SET_CHIP_ACFG_DIS(0x0000),
> - CX25840_SET_CH_1__SOURCE(0x0006),
> - CX25840_SET_CH_2__SOURCE(0x0000),
> - CX25840_SET_CH_3__SOURCE(0x0000), // 1 for 150, 0 for 500
> - CX25840_SET_AUX_PLL_POST(0x0020),
> - CX25840_SET_VID_FMT_SEL(0x0000),
> - CX25840_SET_SQ_PIXEL(0x0000),
> - CX25840_SET_ACFG_DIS(0x0001),
> - CX25840_SET_AFD_PAL_SEL(0x0000),
> - CX25840_SET_AFD_NTSC_SEL(0x0000),
> - CX25840_SET_AUD_MODE_AUD_SYSTEM(0x000f),
> - CX25840_SET_AUD_STANDARD(0x000f),
> - CX25840_SET_PREF_MODE(0x0000),
> - CX25840_SET_MUTE_NO_PREF_MODE(0x0000),
> - CX25840_SET_DE_EMPHASIS_TIME(0x0000),
> - CX25840_SET_FM_DEVIATION(0x0000),
> - CX25840_SET_FORMAT_45MHZ(0x0000),
> - CX25840_SET_FORMAT_65MHZ(0x0002),
> - CX25840_SET_TUNER_OUTPUT_FORMAT(0x0000),
> - CX25840_SET_PATH1_SEL_CTL(0x0000),
> - CX25840_SET_PATH1_AVC_RMS_CON(0x0007),
> - CX25840_SET_PATH1_AVC_CR(0x0000),
> - CX25840_SET_PATH1_AVC_STEREO(0x0001),
> - CX25840_SET_PATH1_AVC_AT(0x0003),
> - CX25840_SET_PATH1_AVC_RT(0x0006),
> - CX25840_SET_PATH1_AVC_CG(0x0000),
> - CX25840_SET_SOFT1_MUTE_EN(0x0000),
> - CX25840_SET_SRC1_MUTE_EN(0x0000),
> - CX25840_SET_SA_MUTE_EN(0x0000),
> - CX25840_SET_PAR_MUTE_EN(0x0000),
> - CX25840_SET_AC97_MUTE_EN(0x0000),
> - CX25840_SET_SRC3_PHASE_INC(41246400/freq_out),
> + CX25840_SET_DUAL_MODE_ADC2(0x0000),
> + CX25840_SET_CH_1__SOURCE(0x0006),
> + CX25840_SET_CH_2__SOURCE(0x0002),
> + CX25840_SET_CH_3__SOURCE(state->input==6?0x0001:0x0000), //
> 1 for 150, 0 for 500
> +
> + CX25840_SET_AUX_PLL_POST(0x0018),
> + CX25840_SET_VID_FMT_SEL(0x0000), // Auto-select video format
> + CX25840_SET_AUD_STANDARD(0x000F), // Force auto-detect of audio
> + CX25840_SET_AUD_MODE_AUD_SYSTEM(0x000F), // Force auto-detect of audio
> + CX25840_SET_PREF_MODE(0x0004), // Preferred audio mode is
> stereo
> + CX25840_SET_MUTE_NO_PREF_MODE(0x0000), // Don't mute if
> preferred output unavailable
> + CX25840_SET_PATH1_SEL_CTL(0x0002), // Set the audio source
> + CX25840_SET_SRC3_PHASE_INC(41942880/freq_out),
> + CX25840_SET_SOFT1_MUTE_EN(0x0001),
> + CX25840_SET_SRC1_MUTE_EN(0x0000),
> + CX25840_SET_SA_MUTE_EN(0x0000),
> + CX25840_SET_PAR_MUTE_EN(0x0001),
> + CX25840_SET_AC97_MUTE_EN(0x0001),
> CX25840_EXECUTE,
>
> - CX25840_SET_START_MICROCNTL(0x0001), // FW Start
> - CX25840_SET_SOFT_RESET(0x0000), // Deassert soft reset
> - CX25840_SET_VD_SOFT_RST(0x0000), // Deassert video reset
> - CX25840_EXECUTE,
> - CX25840_END};
> + CX25840_SET_SOFT_RESET(0x0000), // Deassert soft reset
> + CX25840_SET_VD_SOFT_RST(0x0000), // Deassert video reset
> + CX25840_SET_START_MICROCNTL(0x0001), // FW Start
> + CX25840_EXECUTE,
> + CX25840_END};
>
> setting_sequencer(client, seq);
> break;
> }
> - case 6: {
> - u8 seq[]={
> - CX25840_TAG('T','u','n','n','e','r',' ','1','5','0'),
> -
> - CX25840_SET_START_MICROCNTL(0x0000), // FW stop.
> - CX25840_SET_SOFT_RESET(0x0001), // Soft reset assert.
> - CX25840_SET_VD_SOFT_RST(0x0001), // Video assert
> - CX25840_EXECUTE,
> -
> - CX25840_SET_CH_SEL_ADC2(0x0001),
> - CX25840_SET_DUAL_MODE_ADC2(0x0000),
> - CX25840_SET_CHIP_ACFG_DIS(0x0000),
> - CX25840_SET_CH_1__SOURCE(0x0006),
> - CX25840_SET_CH_2__SOURCE(0x0000),
> - CX25840_SET_CH_3__SOURCE(0x0001), // 1 for 150, 0 for 500
> - CX25840_SET_AUX_PLL_POST(0x0020),
> - CX25840_SET_VID_FMT_SEL(0x0000),
> - CX25840_SET_SQ_PIXEL(0x0000),
> - CX25840_SET_ACFG_DIS(0x0001),
> - CX25840_SET_AFD_PAL_SEL(0x0000),
> - CX25840_SET_AFD_NTSC_SEL(0x0000),
> - CX25840_SET_AUD_MODE_AUD_SYSTEM(0x000f),
> - CX25840_SET_AUD_STANDARD(0x000f),
> - CX25840_SET_PREF_MODE(0x0000),
> - CX25840_SET_MUTE_NO_PREF_MODE(0x0000),
> - CX25840_SET_DE_EMPHASIS_TIME(0x0000),
> - CX25840_SET_FM_DEVIATION(0x0000),
> - CX25840_SET_FORMAT_45MHZ(0x0000),
> - CX25840_SET_FORMAT_65MHZ(0x0002),
> - CX25840_SET_TUNER_OUTPUT_FORMAT(0x0000),
> - CX25840_SET_PATH1_SEL_CTL(0x0000),
> - CX25840_SET_PATH1_AVC_RMS_CON(0x0007),
> - CX25840_SET_PATH1_AVC_CR(0x0000),
> - CX25840_SET_PATH1_AVC_STEREO(0x0001),
> - CX25840_SET_PATH1_AVC_AT(0x0003),
> - CX25840_SET_PATH1_AVC_RT(0x0006),
> - CX25840_SET_PATH1_AVC_CG(0x0000),
> - CX25840_SET_SOFT1_MUTE_EN(0x0000),
> - CX25840_SET_SRC1_MUTE_EN(0x0000),
> - CX25840_SET_SA_MUTE_EN(0x0000),
> - CX25840_SET_PAR_MUTE_EN(0x0000),
> - CX25840_SET_AC97_MUTE_EN(0x0000),
> - CX25840_SET_SRC3_PHASE_INC(41246400/freq_out),
> - CX25840_EXECUTE,
> -
> - CX25840_SET_START_MICROCNTL(0x0001), // FW Start
> - CX25840_SET_SOFT_RESET(0x0000), // Deassert soft reset
> - CX25840_SET_VD_SOFT_RST(0x0000), // Deassert video reset
> - CX25840_EXECUTE,
> - CX25840_END};
> -
> - setting_sequencer(client, seq);
> - break;
> - }
> }
> }
> }
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