From: Antonios Motakis <[email protected]> The AMD Seattle board features SPI ids that are larger than 64, which we do not support properly. This workaround allows us to demonstrate working cells on this target, until we have a proper fix.
This implies that only specific setups will be used on the AMD Seattle; the IRQs for the uart and the second xgmac are being passed to the cells. Signed-off-by: Antonios Motakis <[email protected]> --- hypervisor/arch/arm/irqchip.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/hypervisor/arch/arm/irqchip.c b/hypervisor/arch/arm/irqchip.c index d14de0a..7b9b429 100644 --- a/hypervisor/arch/arm/irqchip.c +++ b/hypervisor/arch/arm/irqchip.c @@ -40,9 +40,22 @@ bool spi_in_cell(struct cell *cell, unsigned int spi) /* FIXME: Change the configuration to a bitmask range */ u32 spi_mask; - if (spi >= 64) + if (spi >= 64) { +#ifdef CONFIG_MACH_AMD_SEATTLE + /* uart irq workaround */ + if (spi == 328) + return (cell != &root_cell); + + /* xgmac1 irq workaround for the very brave. + * Uncommenting this may make the root cell unstable. + if ((spi == 322) || (spi ==324) || + ((spi >= 341) && (spi <= 345))) { + + return (cell != &root_cell); + }*/ +#endif return (cell == &root_cell); - else if (spi >= 32) + } else if (spi >= 32) spi_mask = cell->arch.spis >> 32; else spi_mask = cell->arch.spis; -- 2.8.0.rc3 -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
