On 2016-06-17 21:13, [email protected] wrote:
> From: Antonios Motakis <[email protected]>
> 
> The AMD Seattle board features SPI ids that are larger than 64,
> which we do not support properly. This workaround allows us to
> demonstrate working cells on this target, until we have a proper fix.
> 
> This implies that only specific setups will be used on the
> AMD Seattle; the IRQs for the uart and the second xgmac are being
> passed to the cells.
> 
> Signed-off-by: Antonios Motakis <[email protected]>
> ---
>  hypervisor/arch/arm/irqchip.c | 17 +++++++++++++++--
>  1 file changed, 15 insertions(+), 2 deletions(-)
> 
> diff --git a/hypervisor/arch/arm/irqchip.c b/hypervisor/arch/arm/irqchip.c
> index d14de0a..7b9b429 100644
> --- a/hypervisor/arch/arm/irqchip.c
> +++ b/hypervisor/arch/arm/irqchip.c
> @@ -40,9 +40,22 @@ bool spi_in_cell(struct cell *cell, unsigned int spi)
>       /* FIXME: Change the configuration to a bitmask range */
>       u32 spi_mask;
>  
> -     if (spi >= 64)
> +     if (spi >= 64) {
> +#ifdef CONFIG_MACH_AMD_SEATTLE
> +             /* uart irq workaround */
> +             if (spi == 328)
> +                     return (cell != &root_cell);
> +
> +             /* xgmac1 irq workaround for the very brave.
> +              * Uncommenting this may make the root cell unstable.
> +             if ((spi == 322) || (spi ==324) ||
> +                     ((spi >= 341) && (spi <= 345))) {
> +
> +                     return (cell != &root_cell);
> +             }*/

Ah, this was eating my interrupts! Uncommented, and now it works again.

I was always unbinding the xgmac1 before creating the non-root Linux
cell, plus that interface was down all the time while Jailhouse was
enabled. Therefore no instability here.

Anyway, this is nasty, and we need to address this properly before
merging. In fact, I may have a need for proper SPI assignment on ARM
soon as well. Brings back the proposal I still like most:

> - use multiple irqchip entries per physical chip to add more bitmap
>   capacity if needed
> 
> The latter could be modelled as
> 
> struct jailhouse_irqchip {
>       __u64 address;
>       __u64 id;
>       __u64 pin_base;
>       __u64 pin_bitmap[BITMAP_SIZE];
> }
> 

Let me play with that...

Jan

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