On 2016-07-20 12:07, Marc Zyngier wrote:
> On 20/07/16 10:47, Mark Rutland wrote:
>> Hi Jan,
>>
>> On Wed, Jul 20, 2016 at 10:05:01AM +0100, Marc Zyngier wrote:
>>> On 20/07/16 07:09, Jan Kiszka wrote:
>>>> I've two questions for a while now:
>>>>
>>>> - Are dcache flushes consistently required, or does the MMU snoop
>>>> caches when doing stage-2 translations? We could easily add a
>>>> DCCIMVAC for the modified entries, but I saw KVM flushing even
>>>> page-wise.
>>>
>>> Two things:
>>> - ARMv8 guarantees that the page table walker can snoop the caches,
>>> while we don't have that guarantee on ARMv7, so you need to clean the
>>> cache to the PoC (if memory serves well).
>>
>> For ARMv8-A, as Marc said, walks are guaranteed to be coherent, for both
>> AArch64 and AArch32. For ARMv7-A, walks are guaranteed to be coherent in
>> the presence of the virtualization extensions.
>>
>> In general for ARMv7-A, walks are only coherent (i.e. snoop all
>> data/unified caches) if ID_MMFR3[23:20] ("Coherent Walk") contains
>> 0b0001. See the latest ARM ARM, ARM DDI 0406C.c, section B4.1.92.
>> In other cases, it is necessary to clean to the PoU.
>>
>> The multiprocessing extensions mandate this coherency, per ARM DDI
>> 0406C.c, section B3.3.1 and ARM DDI 0406C.c, section B3.10.1. The
>> virtualization extensions mandate the multiprocessing extensions, per
>> ARM DDI 0406C.c, section B1.7. Thus, in any ARMv7-A implementation with
>> virtualization, page table walks must be coherent.
>
> Ah, I never realized this (3 dependencies to follow is too much for me,
> apparently). I guess I'll go and clean some KVm code now! ;-)
Nice side effect :). Good, then we can change mappings without dcache
flushes as well (minus anything that disabling caches in guest mode
implies). Will focus on BBM now.
Thanks,
Jan
--
Siemens AG, Corporate Technology, CT RDA ITP SES-DE
Corporate Competence Center Embedded Linux
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