We now invalidate/clean the cell caches via MVA, and the driver performs
a MVA-based flush of everything it loads into a cell as well. So we can
safely drop arch_cell_caches_flush as well as arch_cpu_icache_flush that
only this function invokes.
Signed-off-by: Jan Kiszka <jan.kis...@siemens.com>
---
hypervisor/arch/arm/caches.S | 8 --------
hypervisor/arch/arm/control.c | 11 -----------
hypervisor/arch/arm/include/asm/cell.h | 6 ------
hypervisor/arch/arm/include/asm/control.h | 2 --
hypervisor/arch/arm/mmu_cell.c | 26 --------------------------
5 files changed, 53 deletions(-)
diff --git a/hypervisor/arch/arm/caches.S b/hypervisor/arch/arm/caches.S
index f965e6a..c71dea1 100644
--- a/hypervisor/arch/arm/caches.S
+++ b/hypervisor/arch/arm/caches.S
@@ -78,11 +78,3 @@ next_cache:
finish: isb
pop {r0-r11}
bx lr
-
- .global arch_cpu_icache_flush
-arch_cpu_icache_flush:
- dsb
- arm_write_sysreg(ICIALLU, r0) @ r0 value is ignored
- dsb
- isb
- bx lr
diff --git a/hypervisor/arch/arm/control.c b/hypervisor/arch/arm/control.c
index 83add4c..245a87f 100644
--- a/hypervisor/arch/arm/control.c
+++ b/hypervisor/arch/arm/control.c
@@ -98,13 +98,6 @@ void arch_reset_self(struct per_cpu *cpu_data)
err = arm_paging_vcpu_init(cpu_data);
if (err)
printk("MMU setup failed\n");
- /*
- * On the first CPU to reach this, write all cell datas to memory so it
- * can be started with caches disabled.
- * On all CPUs, invalidate the instruction caches to take into account
- * the potential new instructions.
- */
- arch_cell_caches_flush(cell);
/*
* We come from the IRQ handler, but we won't return there, so the IPI
@@ -228,16 +221,12 @@ void arch_resume_cpu(unsigned int cpu_id)
/* CPU must be stopped */
void arch_park_cpu(unsigned int cpu_id)
{
- struct per_cpu *cpu_data = per_cpu(cpu_id);
-
/*
* Reset always follows park_cpu, so we just need to make sure that the
* CPU is suspended
*/
if (psci_wait_cpu_stopped(cpu_id) != 0)
printk("ERROR: CPU%d is supposed to be stopped\n", cpu_id);
- else
- cpu_data->cell->arch.needs_flush = true;
}
/* CPU must be stopped */
diff --git a/hypervisor/arch/arm/include/asm/cell.h
b/hypervisor/arch/arm/include/asm/cell.h
index 696856a..305a2e8 100644
--- a/hypervisor/arch/arm/include/asm/cell.h
+++ b/hypervisor/arch/arm/include/asm/cell.h
@@ -15,22 +15,16 @@
#include <jailhouse/types.h>
#include <asm/smp.h>
-#include <asm/spinlock.h>
#ifndef __ASSEMBLY__
-#include <jailhouse/cell-config.h>
#include <jailhouse/paging.h>
-#include <jailhouse/hypercall.h>
/** ARM-specific cell states. */
struct arch_cell {
struct paging_structures mm;
struct smp_ops *smp;
- spinlock_t caches_lock;
- bool needs_flush;
-
u32 irq_bitmap[1024/32];
unsigned int last_virt_id;
diff --git a/hypervisor/arch/arm/include/asm/control.h
b/hypervisor/arch/arm/include/asm/control.h
index c84a0e3..e901f83 100644
--- a/hypervisor/arch/arm/include/asm/control.h
+++ b/hypervisor/arch/arm/include/asm/control.h
@@ -25,9 +25,7 @@
#include <asm/percpu.h>
void arch_cpu_dcaches_flush(unsigned int action);
-void arch_cpu_icache_flush(void);
void arch_cpu_tlb_flush(struct per_cpu *cpu_data);
-void arch_cell_caches_flush(struct cell *cell);
void arch_handle_sgi(struct per_cpu *cpu_data, u32 irqn);
void arch_handle_trap(struct per_cpu *cpu_data, struct registers *guest_regs);
diff --git a/hypervisor/arch/arm/mmu_cell.c b/hypervisor/arch/arm/mmu_cell.c
index a6a03c9..83ad0f2 100644
--- a/hypervisor/arch/arm/mmu_cell.c
+++ b/hypervisor/arch/arm/mmu_cell.c
@@ -146,29 +146,3 @@ void arch_cpu_tlb_flush(struct per_cpu *cpu_data)
dsb(nsh);
cpu_data->flush_vcpu_caches = false;
}
-
-void arch_cell_caches_flush(struct cell *cell)
-{
- /* Only the first CPU needs to clean the data caches */
- spin_lock(&cell->arch.caches_lock);
- if (cell->arch.needs_flush) {
- /*
- * Since there is no way to know which virtual addresses have
been used
- * by the root cell to write the new cell's data, a complete
clean has
- * to be performed.
- */
- arch_cpu_dcaches_flush(CACHES_CLEAN_INVALIDATE);
- cell->arch.needs_flush = false;
- }
- spin_unlock(&cell->arch.caches_lock);
-
- /*
- * New instructions may have been written, so the I-cache needs to be
- * invalidated even though the VMID is different.
- * A complete invalidation is the only way to ensure all virtual aliases
- * of these memory locations are invalidated, whatever the cache type.
- */
- arch_cpu_icache_flush();
-
- /* ERET will ensure context synchronization */
-}
--
2.1.4
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