On ARM, Linux will update BIST, Latency Timer and Cache Line Size in a single 32-bit write, which includes the Header Type register. This traps so far. But Header Type is specified to be read-only, thus writes have no effect and can safely be allowed as well.
Signed-off-by: Jan Kiszka <[email protected]> --- hypervisor/pci.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hypervisor/pci.c b/hypervisor/pci.c index 8567788..603530f 100644 --- a/hypervisor/pci.c +++ b/hypervisor/pci.c @@ -45,7 +45,8 @@ struct pci_cfg_control { /* Type 1: Endpoints */ static const struct pci_cfg_control endpoint_write[PCI_CONFIG_HEADER_SIZE] = { [0x04/4] = {PCI_CONFIG_ALLOW, 0xffffffff}, /* Command, Status */ - [0x0c/4] = {PCI_CONFIG_ALLOW, 0xff00ffff}, /* BIST, Lat., Cacheline */ + [0x0c/4] = {PCI_CONFIG_ALLOW, 0xffffffff}, /* BIST, Header Type (r/o), + Latency, Cacheline */ [0x30/4] = {PCI_CONFIG_RDONLY, 0xffffffff}, /* ROM BAR */ [0x3c/4] = {PCI_CONFIG_ALLOW, 0x000000ff}, /* Int Line */ }; @@ -55,7 +56,8 @@ static const struct pci_cfg_control endpoint_write[PCI_CONFIG_HEADER_SIZE] = { * perform them on bus rescans. */ static const struct pci_cfg_control bridge_write[PCI_CONFIG_HEADER_SIZE] = { [0x04/4] = {PCI_CONFIG_ALLOW, 0xffffffff}, /* Command, Status */ - [0x0c/4] = {PCI_CONFIG_ALLOW, 0xff00ffff}, /* BIST, Lat., Cacheline */ + [0x0c/4] = {PCI_CONFIG_ALLOW, 0xffffffff}, /* BIST, Header Type (r/o), + Latency, Cacheline */ [0x1c/4] = {PCI_CONFIG_RDONLY, 0x0000ffff}, /* I/O Limit & Base */ [0x20/4 ... /* Memory Limit/Base, Prefetch Memory Limit/Base, */ 0x30/4] = {PCI_CONFIG_RDONLY, 0xffffffff}, /* I/O Limit & Base */ -- 2.1.4 -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
