From: Jan Kiszka <[email protected]> Fall back to INTx in case an ivshmem device comes without MSI-X vectors. This is now implemented for ARM, using standard PCI pin rotation based on the device slot.
x86 has no need for INTx as MSI-X is always supported (plus there is a less uniform legacy INTx injection path which prevents a generic solution). Signed-off-by: Jan Kiszka <[email protected]> --- Changes in v2: - add support for explicit enabling by guest driver - moved generic changes into previous patch 16 hypervisor/arch/arm-common/ivshmem.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/hypervisor/arch/arm-common/ivshmem.c b/hypervisor/arch/arm-common/ivshmem.c index 885d439..14da345 100644 --- a/hypervisor/arch/arm-common/ivshmem.c +++ b/hypervisor/arch/arm-common/ivshmem.c @@ -31,6 +31,9 @@ int arch_ivshmem_update_msix(struct pci_device *device) struct ivshmem_endpoint *ive = device->ivshmem_endpoint; unsigned int irq_id = 0; + if (device->info->num_msix_vectors == 0) + return 0; + if (!ivshmem_is_msix_masked(ive)) { /* FIXME: validate MSI-X target address */ irq_id = device->msix_vectors[0].data; @@ -45,4 +48,12 @@ int arch_ivshmem_update_msix(struct pci_device *device) void arch_ivshmem_update_intx(struct ivshmem_endpoint *ive) { + u8 pin = ive->cspace[PCI_CFG_INT/4] >> 8; + struct pci_device *device = ive->device; + + if (device->info->num_msix_vectors != 0) + return; + + ive->arch.irq_id = (ive->intx_ctrl_reg & IVSHMEM_INTX_ENABLE) ? + (32 + device->cell->config->vpci_irq_base + pin - 1) : 0; } -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
