On 2017-03-19 23:35, Ralf Ramsauer wrote: > Definition of bits of a registers belongs to the definition of the > register itself. Move those definition over to sysregs.h, which is > also shared with inmates that might want to use it. > > No functional change. > > Signed-off-by: Ralf Ramsauer <[email protected]> > --- > hypervisor/arch/arm/include/asm/processor.h | 155 > +------------------------- > hypervisor/arch/arm/include/asm/sysregs.h | 149 +++++++++++++++++++++++++ > hypervisor/arch/arm64/include/asm/processor.h | 131 ---------------------- > hypervisor/arch/arm64/include/asm/sysregs.h | 133 +++++++++++++++++++++- > 4 files changed, 282 insertions(+), 286 deletions(-) > > diff --git a/hypervisor/arch/arm/include/asm/processor.h > b/hypervisor/arch/arm/include/asm/processor.h > index 432c0da872..1ba9e45c96 100644 > --- a/hypervisor/arch/arm/include/asm/processor.h > +++ b/hypervisor/arch/arm/include/asm/processor.h > @@ -15,146 +15,7 @@ > > #include <jailhouse/types.h> > #include <jailhouse/utils.h> > - > -#define PSR_MODE_MASK 0xf > -#define PSR_USR_MODE 0x0 > -#define PSR_FIQ_MODE 0x1 > -#define PSR_IRQ_MODE 0x2 > -#define PSR_SVC_MODE 0x3 > -#define PSR_MON_MODE 0x6 > -#define PSR_ABT_MODE 0x7 > -#define PSR_HYP_MODE 0xa > -#define PSR_UND_MODE 0xb > -#define PSR_SYS_MODE 0xf > - > -#define PSR_32_BIT (1 << 4) > -#define PSR_T_BIT (1 << 5) > -#define PSR_F_BIT (1 << 6) > -#define PSR_I_BIT (1 << 7) > -#define PSR_A_BIT (1 << 8) > -#define PSR_E_BIT (1 << 9) > -#define PSR_J_BIT (1 << 24) > -#define PSR_IT_MASK(it) (((it) & 0x3) << 25 | ((it) & 0xfc) << 8) > -#define PSR_IT(psr) (((psr) >> 25 & 0x3) | ((psr) >> 8 & 0xfc)) > - > -#define RESET_PSR (PSR_I_BIT | PSR_F_BIT | PSR_A_BIT | PSR_SVC_MODE \ > - | PSR_32_BIT) > - > -#define MPIDR_CPUID_MASK 0x00ffffff > -#define MPIDR_MP_BIT (1 << 31) > -#define MPIDR_U_BIT (1 << 30) > - > -#define PFR1_VIRT(pfr) ((pfr) >> 12 & 0xf) > - > -#define SCTLR_M_BIT (1 << 0) > -#define SCTLR_A_BIT (1 << 1) > -#define SCTLR_C_BIT (1 << 2) > -#define SCTLR_CP15B_BIT (1 << 5) > -#define SCTLR_ITD_BIT (1 << 7) > -#define SCTLR_SED_BIT (1 << 8) > -#define SCTLR_I_BIT (1 << 12) > -#define SCTLR_V_BIT (1 << 13) > -#define SCTLR_nTWI (1 << 16) > -#define SCTLR_nTWE (1 << 18) > -#define SCTLR_WXN_BIT (1 << 19) > -#define SCTLR_UWXN_BIT (1 << 20) > -#define SCTLR_FI_BIT (1 << 21) > -#define SCTLR_EE_BIT (1 << 25) > -#define SCTLR_TRE_BIT (1 << 28) > -#define SCTLR_AFE_BIT (1 << 29) > -#define SCTLR_TE_BIT (1 << 30) > - > -#define SCTLR_C_AND_M_SET(sctlr) \ > - (((sctlr) & (SCTLR_C_BIT | SCTLR_M_BIT)) == (SCTLR_C_BIT | SCTLR_M_BIT)) > - > -/* Bits to wipe on cell reset */ > -#define SCTLR_MASK (SCTLR_M_BIT | SCTLR_A_BIT | SCTLR_C_BIT \ > - | SCTLR_I_BIT | SCTLR_V_BIT | SCTLR_WXN_BIT \ > - | SCTLR_UWXN_BIT | SCTLR_FI_BIT | SCTLR_EE_BIT \ > - | SCTLR_TRE_BIT | SCTLR_AFE_BIT | SCTLR_TE_BIT) > - > -#define HCR_TRVM_BIT (1 << 30) > -#define HCR_TVM_BIT (1 << 26) > -#define HCR_HDC_BIT (1 << 29) > -#define HCR_TGE_BIT (1 << 27) > -#define HCR_TTLB_BIT (1 << 25) > -#define HCR_TPU_BIT (1 << 24) > -#define HCR_TPC_BIT (1 << 23) > -#define HCR_TSW_BIT (1 << 22) > -#define HCR_TAC_BIT (1 << 21) > -#define HCR_TIDCP_BIT (1 << 20) > -#define HCR_TSC_BIT (1 << 19) > -#define HCR_TID3_BIT (1 << 18) > -#define HCR_TID2_BIT (1 << 17) > -#define HCR_TID1_BIT (1 << 16) > -#define HCR_TID0_BIT (1 << 15) > -#define HCR_TWE_BIT (1 << 14) > -#define HCR_TWI_BIT (1 << 13) > -#define HCR_DC_BIT (1 << 12) > -#define HCR_BSU_BITS (3 << 10) > -#define HCR_BSU_INNER (1 << 10) > -#define HCR_BSU_OUTER (2 << 10) > -#define HCR_BSU_FULL HCR_BSU_BITS > -#define HCR_FB_BIT (1 << 9) > -#define HCR_VA_BIT (1 << 8) > -#define HCR_VI_BIT (1 << 7) > -#define HCR_VF_BIT (1 << 6) > -#define HCR_AMO_BIT (1 << 5) > -#define HCR_IMO_BIT (1 << 4) > -#define HCR_FMO_BIT (1 << 3) > -#define HCR_PTW_BIT (1 << 2) > -#define HCR_SWIO_BIT (1 << 1) > -#define HCR_VM_BIT (1 << 0) > - > -#define PAR_F_BIT 0x1 > -#define PAR_FST_SHIFT 1 > -#define PAR_FST_MASK 0x3f > -#define PAR_SHA_SHIFT 7 > -#define PAR_SHA_MASK 0x3 > -#define PAR_NS_BIT (0x1 << 9) > -#define PAR_LPAE_BIT (0x1 << 11) > -#define PAR_PA_MASK BIT_MASK(39, 12) > -#define PAR_ATTR_SHIFT 56 > -#define PAR_ATTR_MASK 0xff > - > -/* exception class */ > -#define HSR_EC_SHIFT 26 > -#define HSR_EC(hsr) ((hsr) >> HSR_EC_SHIFT & 0x3f) > -/* instruction length */ > -#define HSR_IL_SHIFT 25 > -#define HSR_IL(hsr) ((hsr) >> HSR_IL_SHIFT & 0x1) > -/* Instruction specific */ > -#define HSR_ICC_MASK 0x1ffffff > -#define HSR_ICC(hsr) ((hsr) & HSR_ICC_MASK) > -/* Exception classes values */ > -#define HSR_EC_UNK 0x00 > -#define HSR_EC_WFI 0x01 > -#define HSR_EC_CP15_32 0x03 > -#define HSR_EC_CP15_64 0x04 > -#define HSR_EC_CP14_32 0x05 > -#define HSR_EC_CP14_LC 0x06 > -#define HSR_EC_HCPTR 0x07 > -#define HSR_EC_CP10 0x08 > -#define HSR_EC_CP14_64 0x0c > -#define HSR_EC_SVC_HYP 0x11 > -#define HSR_EC_HVC 0x12 > -#define HSR_EC_SMC 0x13 > -#define HSR_EC_IABT 0x20 > -#define HSR_EC_IABT_HYP 0x21 > -#define HSR_EC_PCALIGN 0x22 > -#define HSR_EC_DABT 0x24 > -#define HSR_EC_DABT_HYP 0x25 > -/* Condition code */ > -#define HSR_ICC_CV_BIT (1 << 24) > -#define HSR_ICC_COND(icc) ((icc) >> 20 & 0xf) > - > -#define HSR_MATCH_MCR_MRC(hsr, crn, opc1, crm, opc2) \ > - (((hsr) & (BIT_MASK(19, 10) | BIT_MASK(4, 1))) == \ > - (((opc2) << 17) | ((opc1) << 14) | ((crn) << 10) | ((crm) << 1))) > - > -#define HSR_MATCH_MCRR_MRRC(hsr, opc1, crm) \ > - (((hsr) & (BIT_MASK(19, 16) | BIT_MASK(4, 1))) == \ > - (((opc1) << 16) | ((crm) << 1))) > +#include <asm/sysregs.h> > > #define EXIT_REASON_UNDEF 0x1 > #define EXIT_REASON_HVC 0x2 > @@ -178,20 +39,6 @@ struct registers { > #define dsb(domain) asm volatile("dsb " #domain ::: "memory") > #define isb() asm volatile("isb") > > -#define arm_read_banked_reg(reg, val) \ > - asm volatile ("mrs %0, " #reg "\n" : "=r" (val)) > - > -#define arm_write_banked_reg(reg, val) \ > - asm volatile ("msr " #reg ", %0\n" : : "r" (val)) > - > -#define arm_rw_banked_reg(reg, val, is_read) \ > - do { \ > - if (is_read) \ > - arm_read_banked_reg(reg, val); \ > - else \ > - arm_write_banked_reg(reg, val); \ > - } while (0) > - > unsigned int hvc(unsigned int r0, ...); > > static inline void cpu_relax(void) > diff --git a/hypervisor/arch/arm/include/asm/sysregs.h > b/hypervisor/arch/arm/include/asm/sysregs.h > index 9562936035..e65adc45fd 100644 > --- a/hypervisor/arch/arm/include/asm/sysregs.h > +++ b/hypervisor/arch/arm/include/asm/sysregs.h > @@ -25,15 +25,69 @@ > * - arm_read_sysreg(SYSREG_NAME, reg) > */ > > +/* Processor Status Register definitions */ > +#define PSR_MODE_MASK 0xf > +#define PSR_USR_MODE 0x0 > +#define PSR_FIQ_MODE 0x1 > +#define PSR_IRQ_MODE 0x2 > +#define PSR_SVC_MODE 0x3 > +#define PSR_MON_MODE 0x6 > +#define PSR_ABT_MODE 0x7 > +#define PSR_HYP_MODE 0xa > +#define PSR_UND_MODE 0xb > +#define PSR_SYS_MODE 0xf > + > +#define PSR_32_BIT (1 << 4) > +#define PSR_T_BIT (1 << 5) > +#define PSR_F_BIT (1 << 6) > +#define PSR_I_BIT (1 << 7) > +#define PSR_A_BIT (1 << 8) > +#define PSR_E_BIT (1 << 9) > +#define PSR_J_BIT (1 << 24) > +#define PSR_IT_MASK(it) (((it) & 0x3) << 25 | ((it) & 0xfc) << 8) > +#define PSR_IT(psr) (((psr) >> 25 & 0x3) | ((psr) >> 8 & 0xfc)) > + > +#define RESET_PSR (PSR_I_BIT | PSR_F_BIT | PSR_A_BIT | PSR_SVC_MODE \ > + | PSR_32_BIT) > + > /* > * 32bit sysregs definitions > * (Use the AArch64 names to ease the compatibility work) > */ > #define CTR_EL0 SYSREG_32(0, c0, c0, 1) > #define MPIDR_EL1 SYSREG_32(0, c0, c0, 5) > +#define MPIDR_CPUID_MASK 0x00ffffff > +#define MPIDR_MP_BIT (1 << 31) > +#define MPIDR_U_BIT (1 << 30) > #define ID_PFR0_EL1 SYSREG_32(0, c0, c1, 0) > #define ID_PFR1_EL1 SYSREG_32(0, c0, c1, 1) > +#define PFR1_VIRT(pfr) ((pfr) >> 12 & 0xf) > #define SCTLR_EL1 SYSREG_32(0, c1, c0, 0) > +#define SCTLR_M_BIT (1 << 0) > +#define SCTLR_A_BIT (1 << 1) > +#define SCTLR_C_BIT (1 << 2) > +#define SCTLR_CP15B_BIT (1 << 5) > +#define SCTLR_ITD_BIT (1 << 7) > +#define SCTLR_SED_BIT (1 << 8) > +#define SCTLR_I_BIT (1 << 12) > +#define SCTLR_V_BIT (1 << 13) > +#define SCTLR_nTWI (1 << 16) > +#define SCTLR_nTWE (1 << 18) > +#define SCTLR_WXN_BIT (1 << 19) > +#define SCTLR_UWXN_BIT (1 << 20) > +#define SCTLR_FI_BIT (1 << 21) > +#define SCTLR_EE_BIT (1 << 25) > +#define SCTLR_TRE_BIT (1 << 28) > +#define SCTLR_AFE_BIT (1 << 29) > +#define SCTLR_TE_BIT (1 << 30) > +#define SCTLR_C_AND_M_SET(sctlr) \ > + (((sctlr) & (SCTLR_C_BIT | SCTLR_M_BIT)) == (SCTLR_C_BIT | SCTLR_M_BIT)) > + > +/* Bits to wipe on cell reset */ > +#define SCTLR_MASK (SCTLR_M_BIT | SCTLR_A_BIT | SCTLR_C_BIT \ > + | SCTLR_I_BIT | SCTLR_V_BIT | SCTLR_WXN_BIT \ > + | SCTLR_UWXN_BIT | SCTLR_FI_BIT | SCTLR_EE_BIT \ > + | SCTLR_TRE_BIT | SCTLR_AFE_BIT | SCTLR_TE_BIT) > #define ACTLR_EL1 SYSREG_32(0, c1, c0, 1) > #define CPACR_EL1 SYSREG_32(0, c1, c0, 2) > #define CONTEXTIDR_EL1 SYSREG_32(0, c13, c0, 1) > @@ -44,6 +98,45 @@ > #define SCTLR_EL2 SYSREG_32(4, c1, c0, 0) > #define ESR_EL2 SYSREG_32(4, c5, c2, 0) > #define HSR ESR_EL2 /* AArch32 name */ > +/* exception class */ > +#define HSR_EC_SHIFT 26 > +#define HSR_EC(hsr) ((hsr) >> HSR_EC_SHIFT & 0x3f) > +/* instruction length */ > +#define HSR_IL_SHIFT 25 > +#define HSR_IL(hsr) ((hsr) >> HSR_IL_SHIFT & 0x1) > +/* Instruction specific */ > +#define HSR_ICC_MASK 0x1ffffff > +#define HSR_ICC(hsr) ((hsr) & HSR_ICC_MASK) > +/* Exception classes values */ > +#define HSR_EC_UNK 0x00 > +#define HSR_EC_WFI 0x01 > +#define HSR_EC_CP15_32 0x03 > +#define HSR_EC_CP15_64 0x04 > +#define HSR_EC_CP14_32 0x05 > +#define HSR_EC_CP14_LC 0x06 > +#define HSR_EC_HCPTR 0x07 > +#define HSR_EC_CP10 0x08 > +#define HSR_EC_CP14_64 0x0c > +#define HSR_EC_SVC_HYP 0x11 > +#define HSR_EC_HVC 0x12 > +#define HSR_EC_SMC 0x13 > +#define HSR_EC_IABT 0x20 > +#define HSR_EC_IABT_HYP 0x21 > +#define HSR_EC_PCALIGN 0x22 > +#define HSR_EC_DABT 0x24 > +#define HSR_EC_DABT_HYP 0x25 > +/* Condition code */ > +#define HSR_ICC_CV_BIT (1 << 24) > +#define HSR_ICC_COND(icc) ((icc) >> 20 & 0xf) > + > +#define HSR_MATCH_MCR_MRC(hsr, crn, opc1, crm, opc2) \ > + (((hsr) & (BIT_MASK(19, 10) | BIT_MASK(4, 1))) == \ > + (((opc2) << 17) | ((opc1) << 14) | ((crn) << 10) | ((crm) << 1))) > + > +#define HSR_MATCH_MCRR_MRRC(hsr, opc1, crm) \ > + (((hsr) & (BIT_MASK(19, 16) | BIT_MASK(4, 1))) == \ > + (((opc1) << 16) | ((crm) << 1))) > + > #define TPIDR_EL2 SYSREG_32(4, c13, c0, 2) > #define TTBR0_EL2 SYSREG_64(4, c2) > #define TCR_EL2 SYSREG_32(4, c2, c0, 2) > @@ -53,6 +146,16 @@ > #define TTBR0_EL1 SYSREG_64(0, c2) > #define TTBR1_EL1 SYSREG_64(1, c2) > #define PAR_EL1 SYSREG_64(0, c7) > +#define PAR_F_BIT 0x1 > +#define PAR_FST_SHIFT 1 > +#define PAR_FST_MASK 0x3f > +#define PAR_SHA_SHIFT 7 > +#define PAR_SHA_MASK 0x3 > +#define PAR_NS_BIT (0x1 << 9) > +#define PAR_LPAE_BIT (0x1 << 11) > +#define PAR_PA_MASK BIT_MASK(39, 12) > +#define PAR_ATTR_SHIFT 56 > +#define PAR_ATTR_MASK 0xff > > #define CNTKCTL_EL1 SYSREG_32(0, c14, c1, 0) > #define CNTP_TVAL_EL0 SYSREG_32(0, c14, c2, 0) > @@ -73,6 +176,38 @@ > #define VBAR SYSREG_32(0, c12, c0, 0) > #define HCR SYSREG_32(4, c1, c1, 0) > #define HCR2 SYSREG_32(4, c1, c1, 4) > +#define HCR_TRVM_BIT (1 << 30) > +#define HCR_TVM_BIT (1 << 26) > +#define HCR_HDC_BIT (1 << 29) > +#define HCR_TGE_BIT (1 << 27) > +#define HCR_TTLB_BIT (1 << 25) > +#define HCR_TPU_BIT (1 << 24) > +#define HCR_TPC_BIT (1 << 23) > +#define HCR_TSW_BIT (1 << 22) > +#define HCR_TAC_BIT (1 << 21) > +#define HCR_TIDCP_BIT (1 << 20) > +#define HCR_TSC_BIT (1 << 19) > +#define HCR_TID3_BIT (1 << 18) > +#define HCR_TID2_BIT (1 << 17) > +#define HCR_TID1_BIT (1 << 16) > +#define HCR_TID0_BIT (1 << 15) > +#define HCR_TWE_BIT (1 << 14) > +#define HCR_TWI_BIT (1 << 13) > +#define HCR_DC_BIT (1 << 12) > +#define HCR_BSU_BITS (3 << 10) > +#define HCR_BSU_INNER (1 << 10) > +#define HCR_BSU_OUTER (2 << 10) > +#define HCR_BSU_FULL HCR_BSU_BITS > +#define HCR_FB_BIT (1 << 9) > +#define HCR_VA_BIT (1 << 8) > +#define HCR_VI_BIT (1 << 7) > +#define HCR_VF_BIT (1 << 6) > +#define HCR_AMO_BIT (1 << 5) > +#define HCR_IMO_BIT (1 << 4) > +#define HCR_FMO_BIT (1 << 3) > +#define HCR_PTW_BIT (1 << 2) > +#define HCR_SWIO_BIT (1 << 1) > +#define HCR_VM_BIT (1 << 0) > #define HDFAR SYSREG_32(4, c6, c0, 0) > #define HIFAR SYSREG_32(4, c6, c0, 2) > #define HPFAR SYSREG_32(4, c6, c0, 4) > @@ -161,6 +296,20 @@ asm(".arch_extension virt\n"); > asm volatile ("mrrc p15, "#op1", %Q0, %R0, "#crm"\n" \ > : "=r"((u64)(val))) > > +#define arm_read_banked_reg(reg, val) \ > + asm volatile ("mrs %0, " #reg "\n" : "=r" (val)) > + > +#define arm_write_banked_reg(reg, val) \ > + asm volatile ("msr " #reg ", %0\n" : : "r" (val)) > + > +#define arm_rw_banked_reg(reg, val, is_read) \ > + do { \ > + if (is_read) \ > + arm_read_banked_reg(reg, val); \ > + else \ > + arm_write_banked_reg(reg, val); \ > + } while (0) > + > #else /* __ASSEMBLY__ */ > > #define arm_write_sysreg_32(op1, crn, crm, op2, reg) \ > diff --git a/hypervisor/arch/arm64/include/asm/processor.h > b/hypervisor/arch/arm64/include/asm/processor.h > index d4428297e3..00b8601b74 100644 > --- a/hypervisor/arch/arm64/include/asm/processor.h > +++ b/hypervisor/arch/arm64/include/asm/processor.h > @@ -16,143 +16,12 @@ > #include <jailhouse/types.h> > #include <jailhouse/utils.h> > > -#define PSR_MODE_MASK 0xf > -#define PSR_MODE_EL0t 0x0 > -#define PSR_MODE_EL1t 0x4 > -#define PSR_MODE_EL1h 0x5 > -#define PSR_MODE_EL2t 0x8 > -#define PSR_MODE_EL2h 0x9 > - > -#define PSR_F_BIT (1 << 6) > -#define PSR_I_BIT (1 << 7) > -#define PSR_A_BIT (1 << 8) > -#define PSR_D_BIT (1 << 9) > -#define PSR_IL_BIT (1 << 20) > -#define PSR_SS_BIT (1 << 21) > -#define RESET_PSR (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT \ > - | PSR_MODE_EL1h) > - > -#define MPIDR_CPUID_MASK 0xff00ffffff > -#define MPIDR_MP_BIT (1 << 31) > -#define MPIDR_U_BIT (1 << 30) > - > -#define SCTLR_M_BIT (1 << 0) > -#define SCTLR_A_BIT (1 << 1) > -#define SCTLR_C_BIT (1 << 2) > -#define SCTLR_SA_BIT (1 << 3) > -#define SCTLR_SA0_BIT (1 << 4) > -#define SCTLR_CP15B_BIT (1 << 5) > -#define SCTLR_ITD_BIT (1 << 7) > -#define SCTLR_SED_BIT (1 << 8) > -#define SCTLR_UMA_BIT (1 << 9) > -#define SCTLR_I_BIT (1 << 12) > -#define SCTLR_DZE_BIT (1 << 14) > -#define SCTLR_UCT_BIT (1 << 15) > -#define SCTLR_nTWI (1 << 16) > -#define SCTLR_nTWE (1 << 18) > -#define SCTLR_WXN_BIT (1 << 19) > -#define SCTLR_E0E_BIT (1 << 24) > -#define SCTLR_EE_BIT (1 << 25) > -#define SCTLR_UCI_BIT (1 << 26) > - > -#define SCTLR_EL1_RES1 ((1 << 11) | (1 << 20) | (3 << 22) | (3 << 28)) > -#define SCTLR_EL2_RES1 ((3 << 4) | (1 << 11) | (1 << 16) | (1 << 18) > \ > - | (3 << 22) | (3 << 28)) > - > -#define HCR_MIOCNCE_BIT (1u << 38) > -#define HCR_ID_BIT (1u << 33) > -#define HCR_CD_BIT (1u << 32) > -#define HCR_RW_BIT (1u << 31) > -#define HCR_TRVM_BIT (1u << 30) > -#define HCR_HDC_BIT (1u << 29) > -#define HCR_TDZ_BIT (1u << 28) > -#define HCR_TGE_BIT (1u << 27) > -#define HCR_TVM_BIT (1u << 26) > -#define HCR_TTLB_BIT (1u << 25) > -#define HCR_TPU_BIT (1u << 24) > -#define HCR_TPC_BIT (1u << 23) > -#define HCR_TSW_BIT (1u << 22) > -#define HCR_TAC_BIT (1u << 21) > -#define HCR_TIDCP_BIT (1u << 20) > -#define HCR_TSC_BIT (1u << 19) > -#define HCR_TID3_BIT (1u << 18) > -#define HCR_TID2_BIT (1u << 17) > -#define HCR_TID1_BIT (1u << 16) > -#define HCR_TID0_BIT (1u << 15) > -#define HCR_TWE_BIT (1u << 14) > -#define HCR_TWI_BIT (1u << 13) > -#define HCR_DC_BIT (1u << 12) > -#define HCR_BSU_BITS (3u << 10) > -#define HCR_BSU_INNER (1u << 10) > -#define HCR_BSU_OUTER (2u << 10) > -#define HCR_BSU_FULL HCR_BSU_BITS > -#define HCR_FB_BIT (1u << 9) > -#define HCR_VA_BIT (1u << 8) > -#define HCR_VI_BIT (1u << 7) > -#define HCR_VF_BIT (1u << 6) > -#define HCR_AMO_BIT (1u << 5) > -#define HCR_IMO_BIT (1u << 4) > -#define HCR_FMO_BIT (1u << 3) > -#define HCR_PTW_BIT (1u << 2) > -#define HCR_SWIO_BIT (1u << 1) > -#define HCR_VM_BIT (1u << 0) > - > -/* exception class */ > -#define ESR_EC_SHIFT 26 > -#define ESR_EC(hsr) ((hsr) >> ESR_EC_SHIFT & 0x3f) > -/* instruction length */ > -#define ESR_IL_SHIFT 25 > -#define ESR_IL(hsr) ((hsr) >> ESR_IL_SHIFT & 0x1) > -/* Instruction specific syndrom */ > -#define ESR_ISS_MASK 0x1ffffff > -#define ESR_ISS(esr) ((esr) & ESR_ISS_MASK) > -/* Exception classes values */ > -#define ESR_EC_UNKNOWN 0x00 > -#define ESR_EC_WFx 0x01 > -#define ESR_EC_CP15_32 0x03 > -#define ESR_EC_CP15_64 0x04 > -#define ESR_EC_CP14_MR 0x05 > -#define ESR_EC_CP14_LS 0x06 > -#define ESR_EC_FP_ASIMD 0x07 > -#define ESR_EC_CP10_ID 0x08 > -#define ESR_EC_CP14_64 0x0C > -#define ESR_EC_ILL 0x0E > -#define ESR_EC_SVC32 0x11 > -#define ESR_EC_HVC32 0x12 > -#define ESR_EC_SMC32 0x13 > -#define ESR_EC_SVC64 0x15 > -#define ESR_EC_HVC64 0x16 > -#define ESR_EC_SMC64 0x17 > -#define ESR_EC_SYS64 0x18 > -#define ESR_EC_IMP_DEF 0x1f > -#define ESR_EC_IABT_LOW 0x20 > -#define ESR_EC_IABT_CUR 0x21 > -#define ESR_EC_PC_ALIGN 0x22 > -#define ESR_EC_DABT_LOW 0x24 > -#define ESR_EC_DABT_CUR 0x25 > -#define ESR_EC_SP_ALIGN 0x26 > -#define ESR_EC_FP_EXC32 0x28 > -#define ESR_EC_FP_EXC64 0x2C > -#define ESR_EC_SERROR 0x2F > -#define ESR_EC_BREAKPT_LOW 0x30 > -#define ESR_EC_BREAKPT_CUR 0x31 > -#define ESR_EC_SOFTSTP_LOW 0x32 > -#define ESR_EC_SOFTSTP_CUR 0x33 > -#define ESR_EC_WATCHPT_LOW 0x34 > -#define ESR_EC_WATCHPT_CUR 0x35 > -#define ESR_EC_BKPT32 0x38 > -#define ESR_EC_VECTOR32 0x3A > -#define ESR_EC_BRK64 0x3C > - > #define EXIT_REASON_EL2_ABORT 0x0 > #define EXIT_REASON_EL1_ABORT 0x1 > #define EXIT_REASON_EL1_IRQ 0x2 > > #define NUM_USR_REGS 31 > > -/* exception level in SPSR_ELx */ > -#define SPSR_EL(spsr) (((spsr) & 0xc) >> 2) > - > #ifndef __ASSEMBLY__ > > struct registers { > diff --git a/hypervisor/arch/arm64/include/asm/sysregs.h > b/hypervisor/arch/arm64/include/asm/sysregs.h > index fa13ea316c..d0f8fa37ac 100644 > --- a/hypervisor/arch/arm64/include/asm/sysregs.h > +++ b/hypervisor/arch/arm64/include/asm/sysregs.h > @@ -13,6 +13,137 @@ > #ifndef _JAILHOUSE_ASM_SYSREGS_H > #define _JAILHOUSE_ASM_SYSREGS_H > > +#define PSR_MODE_MASK 0xf > +#define PSR_MODE_EL0t 0x0 > +#define PSR_MODE_EL1t 0x4 > +#define PSR_MODE_EL1h 0x5 > +#define PSR_MODE_EL2t 0x8 > +#define PSR_MODE_EL2h 0x9 > + > +#define PSR_F_BIT (1 << 6) > +#define PSR_I_BIT (1 << 7) > +#define PSR_A_BIT (1 << 8) > +#define PSR_D_BIT (1 << 9) > +#define PSR_IL_BIT (1 << 20) > +#define PSR_SS_BIT (1 << 21) > +#define RESET_PSR (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT \ > + | PSR_MODE_EL1h) > + > +#define MPIDR_CPUID_MASK 0xff00ffffff > +#define MPIDR_MP_BIT (1 << 31) > +#define MPIDR_U_BIT (1 << 30) > + > +#define SCTLR_M_BIT (1 << 0) > +#define SCTLR_A_BIT (1 << 1) > +#define SCTLR_C_BIT (1 << 2) > +#define SCTLR_SA_BIT (1 << 3) > +#define SCTLR_SA0_BIT (1 << 4) > +#define SCTLR_CP15B_BIT (1 << 5) > +#define SCTLR_ITD_BIT (1 << 7) > +#define SCTLR_SED_BIT (1 << 8) > +#define SCTLR_UMA_BIT (1 << 9) > +#define SCTLR_I_BIT (1 << 12) > +#define SCTLR_DZE_BIT (1 << 14) > +#define SCTLR_UCT_BIT (1 << 15) > +#define SCTLR_nTWI (1 << 16) > +#define SCTLR_nTWE (1 << 18) > +#define SCTLR_WXN_BIT (1 << 19) > +#define SCTLR_E0E_BIT (1 << 24) > +#define SCTLR_EE_BIT (1 << 25) > +#define SCTLR_UCI_BIT (1 << 26) > + > +#define SCTLR_EL1_RES1 ((1 << 11) | (1 << 20) | (3 << 22) | (3 << 28)) > +#define SCTLR_EL2_RES1 ((3 << 4) | (1 << 11) | (1 << 16) | (1 << 18) > \ > + | (3 << 22) | (3 << 28)) > + > +#define HCR_MIOCNCE_BIT (1u << 38) > +#define HCR_ID_BIT (1u << 33) > +#define HCR_CD_BIT (1u << 32) > +#define HCR_RW_BIT (1u << 31) > +#define HCR_TRVM_BIT (1u << 30) > +#define HCR_HDC_BIT (1u << 29) > +#define HCR_TDZ_BIT (1u << 28) > +#define HCR_TGE_BIT (1u << 27) > +#define HCR_TVM_BIT (1u << 26) > +#define HCR_TTLB_BIT (1u << 25) > +#define HCR_TPU_BIT (1u << 24) > +#define HCR_TPC_BIT (1u << 23) > +#define HCR_TSW_BIT (1u << 22) > +#define HCR_TAC_BIT (1u << 21) > +#define HCR_TIDCP_BIT (1u << 20) > +#define HCR_TSC_BIT (1u << 19) > +#define HCR_TID3_BIT (1u << 18) > +#define HCR_TID2_BIT (1u << 17) > +#define HCR_TID1_BIT (1u << 16) > +#define HCR_TID0_BIT (1u << 15) > +#define HCR_TWE_BIT (1u << 14) > +#define HCR_TWI_BIT (1u << 13) > +#define HCR_DC_BIT (1u << 12) > +#define HCR_BSU_BITS (3u << 10) > +#define HCR_BSU_INNER (1u << 10) > +#define HCR_BSU_OUTER (2u << 10) > +#define HCR_BSU_FULL HCR_BSU_BITS > +#define HCR_FB_BIT (1u << 9) > +#define HCR_VA_BIT (1u << 8) > +#define HCR_VI_BIT (1u << 7) > +#define HCR_VF_BIT (1u << 6) > +#define HCR_AMO_BIT (1u << 5) > +#define HCR_IMO_BIT (1u << 4) > +#define HCR_FMO_BIT (1u << 3) > +#define HCR_PTW_BIT (1u << 2) > +#define HCR_SWIO_BIT (1u << 1) > +#define HCR_VM_BIT (1u << 0) > + > +/* exception class */ > +#define ESR_EC_SHIFT 26 > +#define ESR_EC(hsr) ((hsr) >> ESR_EC_SHIFT & 0x3f) > +/* instruction length */ > +#define ESR_IL_SHIFT 25 > +#define ESR_IL(hsr) ((hsr) >> ESR_IL_SHIFT & 0x1) > +/* Instruction specific syndrom */ > +#define ESR_ISS_MASK 0x1ffffff > +#define ESR_ISS(esr) ((esr) & ESR_ISS_MASK) > +/* Exception classes values */ > +#define ESR_EC_UNKNOWN 0x00 > +#define ESR_EC_WFx 0x01 > +#define ESR_EC_CP15_32 0x03 > +#define ESR_EC_CP15_64 0x04 > +#define ESR_EC_CP14_MR 0x05 > +#define ESR_EC_CP14_LS 0x06 > +#define ESR_EC_FP_ASIMD 0x07 > +#define ESR_EC_CP10_ID 0x08 > +#define ESR_EC_CP14_64 0x0C > +#define ESR_EC_ILL 0x0E > +#define ESR_EC_SVC32 0x11 > +#define ESR_EC_HVC32 0x12 > +#define ESR_EC_SMC32 0x13 > +#define ESR_EC_SVC64 0x15 > +#define ESR_EC_HVC64 0x16 > +#define ESR_EC_SMC64 0x17 > +#define ESR_EC_SYS64 0x18 > +#define ESR_EC_IMP_DEF 0x1f > +#define ESR_EC_IABT_LOW 0x20 > +#define ESR_EC_IABT_CUR 0x21 > +#define ESR_EC_PC_ALIGN 0x22 > +#define ESR_EC_DABT_LOW 0x24 > +#define ESR_EC_DABT_CUR 0x25 > +#define ESR_EC_SP_ALIGN 0x26 > +#define ESR_EC_FP_EXC32 0x28 > +#define ESR_EC_FP_EXC64 0x2C > +#define ESR_EC_SERROR 0x2F > +#define ESR_EC_BREAKPT_LOW 0x30 > +#define ESR_EC_BREAKPT_CUR 0x31 > +#define ESR_EC_SOFTSTP_LOW 0x32 > +#define ESR_EC_SOFTSTP_CUR 0x33 > +#define ESR_EC_WATCHPT_LOW 0x34 > +#define ESR_EC_WATCHPT_CUR 0x35 > +#define ESR_EC_BKPT32 0x38 > +#define ESR_EC_VECTOR32 0x3A > +#define ESR_EC_BRK64 0x3C > + > +/* exception level in SPSR_ELx */ > +#define SPSR_EL(spsr) (((spsr) & 0xc) >> 2) > + > #ifndef __ASSEMBLY__ > > #define arm_write_sysreg(sysreg, val) \ > @@ -21,6 +152,6 @@ > #define arm_read_sysreg(sysreg, val) \ > asm volatile ("mrs %0, "#sysreg"\n" : "=r"((u64)(val))) > > -#endif > +#endif /* __ASSEMBLY__ */ > > #endif >
Merged, thanks. Jan -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
