ICH_LRC is available in aarch32 state In aarch64 state, ICH_LR is a 64bit system register Writing to ICH_LRC generates exception, remove it
Signed-off-by: Nikhil Devshatwar <[email protected]> --- hypervisor/arch/arm-common/include/asm/gic_v3.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/hypervisor/arch/arm-common/include/asm/gic_v3.h b/hypervisor/arch/arm-common/include/asm/gic_v3.h index 1fcd5a4..cac47db 100644 --- a/hypervisor/arch/arm-common/include/asm/gic_v3.h +++ b/hypervisor/arch/arm-common/include/asm/gic_v3.h @@ -226,13 +226,11 @@ static inline u64 gic_read_lr(unsigned int n) static inline void gic_write_lr(unsigned int n, u64 val) { u32 lr = (u32)val; - u32 lrc = val >> 32; switch (n) { #define __WRITE_LR(n) \ case n: \ arm_write_sysreg(ICH_LR##n, lr); \ - arm_write_sysreg(ICH_LRC##n, lrc); \ break; __WRITE_LR(0) -- 1.9.1 -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
