On 2017-07-23 09:54, Devshatwar, Nikhil wrote:
>>> This series is an attempt to get jailhouse working on systems with
>>> 64bit CPUs and non GIC v3 (non v2 compatible)
>>>
>>> With my half knowledge, I have tried to get a few things working.
>>> I might have fixed one and broke ten others.
>>> Please scrutinize each change and point out issues.
>>>
>>> ONLY tested with aarch64 and GICv3 config
>>>
>>
>> Umm, did this really work in the simulator?
>>
>> SMP is broken because the access that gicv3_handle_sgir_write handles is not
>> forwarded out. Consequently, I'm getting unhandled traps on "msr
>> s3_0_c12_c11_5, x25".
>>
>> But even when I disable SMP (taking one core offline, configuring only the
>> remaining one), the ESPRESSObin freezes after enabling. I can't exclude a
>> board-
>> specific issue yet, need to debug.
>
> Yes, this is exactly the problems I am currently debugging.
> With SMP, I am getting unhandled traps for SGI writes issued by kernel
> Without SMP, none of the IRQs are getting delivered to kernel, hence kernel
> is waiting for WFI forever.
> Even UART IRQs are not getting forwarded.
That's fixed now, but I need to cross-check if 32-bit ARM still builds
at least:
diff --git a/hypervisor/arch/arm-common/include/asm/gic_v3.h
b/hypervisor/arch/arm-common/include/asm/gic_v3.h
index 1fcd5a41..ade80cde 100644
--- a/hypervisor/arch/arm-common/include/asm/gic_v3.h
+++ b/hypervisor/arch/arm-common/include/asm/gic_v3.h
@@ -189,13 +189,12 @@
static inline u64 gic_read_lr(unsigned int n)
{
- u32 lr, lrc;
+ u64 lr;
switch (n) {
#define __READ_LR(n) \
case n: \
arm_read_sysreg(ICH_LR##n, lr); \
- arm_read_sysreg(ICH_LRC##n, lrc); \
break;
__READ_LR(0)
@@ -220,19 +219,15 @@ static inline u64 gic_read_lr(unsigned int n)
return (u64)(-1);
}
- return (u64)lrc << 32 | lr;
+ return lr;
}
static inline void gic_write_lr(unsigned int n, u64 val)
{
- u32 lr = (u32)val;
- u32 lrc = val >> 32;
-
switch (n) {
#define __WRITE_LR(n) \
case n: \
- arm_write_sysreg(ICH_LR##n, lr); \
- arm_write_sysreg(ICH_LRC##n, lrc); \
+ arm_write_sysreg(ICH_LR##n, val); \
break;
__WRITE_LR(0)
>
> I'll try to use the gicv3_handle_sgir_write and see if it helps
That should address the SMP issue. And then we would be able to start a
non-root cell as well.
Preparing my changes for next right now.
Jan
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