Branch: refs/heads/next
Home: https://github.com/siemens/jailhouse
Commit: ff20a79ce86b6e691982e41465b7f2a53eb8df85
https://github.com/siemens/jailhouse/commit/ff20a79ce86b6e691982e41465b7f2a53eb8df85
Author: Ralf Ramsauer <[email protected]>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M configs/jetson-tx1-demo.c
M configs/jetson-tx1.c
Log Message:
-----------
configs: TX1: add support for virtual PCI device
By placing the IVSHMEM region right before the HV memory.
Signed-off-by: Ralf Ramsauer <[email protected]>
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 057250e976589e53e75e4680f5c74649cbeb53a3
https://github.com/siemens/jailhouse/commit/057250e976589e53e75e4680f5c74649cbeb53a3
Author: Ralf Ramsauer <[email protected]>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
A configs/dts/inmate-jetson-tx1.dts
A configs/jetson-tx1-linux-demo.c
Log Message:
-----------
configs: Add Jetson TX1 Linux demo config
Uses the primary UART console as shared device, but the interrupt will
be redirected to the non-root Linux cell.
IVSHMEM virtual PCI device is enabled.
Signed-off-by: Ralf Ramsauer <[email protected]>
Signed-off-by: Jan Kiszka <[email protected]>
Commit: d2337c0afd07db6dd11deb68dea67f729750d77b
https://github.com/siemens/jailhouse/commit/d2337c0afd07db6dd11deb68dea67f729750d77b
Author: Ralf Ramsauer <[email protected]>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M hypervisor/arch/arm-common/include/asm/gic_v2.h
M hypervisor/arch/arm-common/irqchip.c
M hypervisor/arch/arm/include/asm/gic_v3.h
Log Message:
-----------
arm: rename gic_read_iar to gic_read_iar_irqn
Currently, gic_read_iar is only used to read the irqn. Additionally,
gic_read_iar implementation for arm applies a mask that hides some bits
of the IAR register.
Let's rename gic_read_iar to gic_read_iar_irqn to make it more obvious
what this function actually does.
Signed-off-by: Ralf Ramsauer <[email protected]>
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 8f5ec01dc1ccb5d7c9431b6da47b31cff31c44bf
https://github.com/siemens/jailhouse/commit/8f5ec01dc1ccb5d7c9431b6da47b31cff31c44bf
Author: Ralf Ramsauer <[email protected]>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M hypervisor/arch/arm/include/asm/gic_v3.h
Log Message:
-----------
arm: hide reserved bits when reading GICv3's IAR
Bits [31:24] are reserved. Hide them when reading the irqn.
Signed-off-by: Ralf Ramsauer <[email protected]>
Signed-off-by: Jan Kiszka <[email protected]>
Commit: fece51aa2157597c59bba2f28197c77c76354d43
https://github.com/siemens/jailhouse/commit/fece51aa2157597c59bba2f28197c77c76354d43
Author: Jan Kiszka <[email protected]>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M hypervisor/arch/arm-common/irqchip.c
Log Message:
-----------
arm-common: Remove redundant zero-initialization
Global variables are always zero-initialized.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 249192b55de0cb753278506534334738397d5780
https://github.com/siemens/jailhouse/commit/249192b55de0cb753278506534334738397d5780
Author: Jan Kiszka <[email protected]>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M hypervisor/arch/arm-common/irqchip.c
Log Message:
-----------
arm-common: Remove redundant statement for SGI routing mode 2
In case of mode 2, the targets field won't be evaluated. So we can safe
one statement and rather invest in explaining when we need to adjust
targets.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 0735f1a56992570dcf80555aebe2d9579cf4fe56
https://github.com/siemens/jailhouse/commit/0735f1a56992570dcf80555aebe2d9579cf4fe56
Author: Jan Kiszka <[email protected]>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M hypervisor/arch/arm-common/irqchip.c
Log Message:
-----------
arm-common: Clearify the role of gicv2_target_cpu_map in GICv3 mode
What we do on GICD_SGIR in GICv3 mode with affinity routing on is not
obvious. Leave a comment.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 94ce5e366c14e0985cb6cb583a550bb5908e7dbc
https://github.com/siemens/jailhouse/commit/94ce5e366c14e0985cb6cb583a550bb5908e7dbc
Author: Jan Kiszka <[email protected]>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M hypervisor/arch/arm/control.c
M hypervisor/arch/arm/gic-v3.c
M hypervisor/arch/arm/include/asm/cell.h
Log Message:
-----------
arm: Declare each redistributor region to be last
As long as we are virtualizing MPIDR and, thus, also the region layout,
we can easily mark the end. However, when removing this virtualization
and starting to hand out the regions as-is, it will become complex to
identify contiguous ones.
To make this simple (for the hypervisor), just declare each of them to
be last. That means we will have to construct device trees for non-root
cells that declare multiple redistributor regions, even if they are
physically contiguous.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: cc42036c596e170ac661ae74022ca1a5054499eb
https://github.com/siemens/jailhouse/commit/cc42036c596e170ac661ae74022ca1a5054499eb
Author: Jan Kiszka <[email protected]>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M hypervisor/arch/arm/gic-v3.c
Log Message:
-----------
arm: Switch redistributor handling completely to MMIO dispatcher
We can avoid the extra loop in gic_handle_redist_access just to map the
virtual GICR address to its corresponding CPU. We just need to register
one redist region per cell CPU.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: ee06c3687fcbb0de9c244d964dfa8b6272bcf056
https://github.com/siemens/jailhouse/commit/ee06c3687fcbb0de9c244d964dfa8b6272bcf056
Author: Jan Kiszka <[email protected]>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M hypervisor/arch/arm/gic-v3.c
M hypervisor/arch/arm/include/asm/sysregs.h
Log Message:
-----------
arm: Detect unsupported Aff0 values in MPIDR
Just to be safe: ICC_SGI1R_EL1 allows us to address at most 16 cores in
the most significant affinity level. Encode this restriction in the init
code because we will rely on it during runtime.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 92c6ece091634279b2abe940c273430f0f854183
https://github.com/siemens/jailhouse/commit/92c6ece091634279b2abe940c273430f0f854183
Author: Jan Kiszka <[email protected]>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M hypervisor/arch/arm/gic-v3.c
M hypervisor/arch/arm/include/asm/percpu.h
Log Message:
-----------
arm: Move gicr per-cpu parameter into struct
This prepares for adding another GICv3 parameter later on.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 1a1ed32f24594e8d7aa12cae2fc0cc2ad4f1d2d2
https://github.com/siemens/jailhouse/commit/1a1ed32f24594e8d7aa12cae2fc0cc2ad4f1d2d2
Author: Jan Kiszka <[email protected]>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M hypervisor/arch/arm/gic-v3.c
M hypervisor/arch/arm/include/asm/percpu.h
Log Message:
-----------
arm: Track physical address of redistributors for each CPU
We will need this once we start to identity-map the redistributors. And
while we could currently still calculate the addresses, better prepare
for multiple redist regions and store the address along the mapping.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 137d5c2d04f2f0a09a454d4ae72e184cb6382583
https://github.com/siemens/jailhouse/commit/137d5c2d04f2f0a09a454d4ae72e184cb6382583
Author: Jan Kiszka <[email protected]>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M configs/dts/inmate-bananapi.dts
M configs/dts/inmate-jetson-tk1.dts
M configs/dts/inmate-orangepi0.dts
M hypervisor/arch/arm-common/include/asm/gic.h
M hypervisor/arch/arm-common/irqchip.c
M hypervisor/arch/arm/control.c
M hypervisor/arch/arm/gic-v3.c
M hypervisor/arch/arm/include/asm/sysregs.h
M hypervisor/arch/arm64/include/asm/sysregs.h
Log Message:
-----------
arm: Remove MPIDR virtualization
Do not modify the MPIDR value that the cells see. VMPIDR is initialized
to the physical MPIDR on reset, and we can safely keep this, even while
the GICv2 IDs are still virtualized because they are unrelated.
We just need to adjust the GICv3 case because there we are in affinity
routing mode, and the MPIDR does play a role when dispatching SGIs.
GICR_TYPER can now be kept almost unmodified. Moreover, the
redistributors needs to be identity-mapped into the guests.
This also aligns arm with arm64 and will help introducing GICv3 to the
latter.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: ca34dd09caea5206b587761789e17b6cde437722
https://github.com/siemens/jailhouse/commit/ca34dd09caea5206b587761789e17b6cde437722
Author: Jan Kiszka <[email protected]>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M hypervisor/arch/arm-common/irqchip.c
M hypervisor/arch/arm/control.c
M hypervisor/arch/arm/include/asm/percpu.h
M hypervisor/arch/arm/setup.c
M hypervisor/arch/arm64/control.c
M hypervisor/arch/arm64/include/asm/percpu.h
Log Message:
-----------
arm, arm64: Remove remaining traces of virt_id
No more users of arm_cpu_phys2virt/virt2phys are remaining, so we can
purge the code from related fragments.
Signed-off-by: Jan Kiszka <[email protected]>
Compare:
https://github.com/siemens/jailhouse/compare/61f738d2740b...ca34dd09caea
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