Branch: refs/heads/coverity_scan
Home: https://github.com/siemens/jailhouse
Commit: ff20a79ce86b6e691982e41465b7f2a53eb8df85
https://github.com/siemens/jailhouse/commit/ff20a79ce86b6e691982e41465b7f2a53eb8df85
Author: Ralf Ramsauer <[email protected]>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M configs/jetson-tx1-demo.c
M configs/jetson-tx1.c
Log Message:
-----------
configs: TX1: add support for virtual PCI device
By placing the IVSHMEM region right before the HV memory.
Signed-off-by: Ralf Ramsauer <[email protected]>
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 057250e976589e53e75e4680f5c74649cbeb53a3
https://github.com/siemens/jailhouse/commit/057250e976589e53e75e4680f5c74649cbeb53a3
Author: Ralf Ramsauer <[email protected]>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
A configs/dts/inmate-jetson-tx1.dts
A configs/jetson-tx1-linux-demo.c
Log Message:
-----------
configs: Add Jetson TX1 Linux demo config
Uses the primary UART console as shared device, but the interrupt will
be redirected to the non-root Linux cell.
IVSHMEM virtual PCI device is enabled.
Signed-off-by: Ralf Ramsauer <[email protected]>
Signed-off-by: Jan Kiszka <[email protected]>
Commit: d2337c0afd07db6dd11deb68dea67f729750d77b
https://github.com/siemens/jailhouse/commit/d2337c0afd07db6dd11deb68dea67f729750d77b
Author: Ralf Ramsauer <[email protected]>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M hypervisor/arch/arm-common/include/asm/gic_v2.h
M hypervisor/arch/arm-common/irqchip.c
M hypervisor/arch/arm/include/asm/gic_v3.h
Log Message:
-----------
arm: rename gic_read_iar to gic_read_iar_irqn
Currently, gic_read_iar is only used to read the irqn. Additionally,
gic_read_iar implementation for arm applies a mask that hides some bits
of the IAR register.
Let's rename gic_read_iar to gic_read_iar_irqn to make it more obvious
what this function actually does.
Signed-off-by: Ralf Ramsauer <[email protected]>
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 8f5ec01dc1ccb5d7c9431b6da47b31cff31c44bf
https://github.com/siemens/jailhouse/commit/8f5ec01dc1ccb5d7c9431b6da47b31cff31c44bf
Author: Ralf Ramsauer <[email protected]>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M hypervisor/arch/arm/include/asm/gic_v3.h
Log Message:
-----------
arm: hide reserved bits when reading GICv3's IAR
Bits [31:24] are reserved. Hide them when reading the irqn.
Signed-off-by: Ralf Ramsauer <[email protected]>
Signed-off-by: Jan Kiszka <[email protected]>
Commit: fece51aa2157597c59bba2f28197c77c76354d43
https://github.com/siemens/jailhouse/commit/fece51aa2157597c59bba2f28197c77c76354d43
Author: Jan Kiszka <[email protected]>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M hypervisor/arch/arm-common/irqchip.c
Log Message:
-----------
arm-common: Remove redundant zero-initialization
Global variables are always zero-initialized.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: a934d651e94f06acfd5bcce096ca673592f7e505
https://github.com/siemens/jailhouse/commit/a934d651e94f06acfd5bcce096ca673592f7e505
Author: Jan Kiszka <[email protected]>
Date: 2017-09-05 (Tue, 05 Sep 2017)
Changed paths:
M hypervisor/arch/arm-common/irqchip.c
Log Message:
-----------
arm-common: Remove redundant statement for SGI routing mode 2
In case of mode 2, the targets field won't be evaluated. So we can save
one statement, initialized targets to 0 unconditionally, and instead
invest in explaining when we need to tune it further.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 68ee1d6a7fdb8d51607c4c9ee92b12b817171c1f
https://github.com/siemens/jailhouse/commit/68ee1d6a7fdb8d51607c4c9ee92b12b817171c1f
Author: Jan Kiszka <[email protected]>
Date: 2017-09-05 (Tue, 05 Sep 2017)
Changed paths:
M hypervisor/arch/arm-common/irqchip.c
Log Message:
-----------
arm-common: Clearify the role of gicv2_target_cpu_map in GICv3 mode
What we do on GICD_SGIR in GICv3 mode with affinity routing on is not
obvious. Leave a comment.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 4dcbd9d842148bb627918f52e5472afa7a558f7a
https://github.com/siemens/jailhouse/commit/4dcbd9d842148bb627918f52e5472afa7a558f7a
Author: Jan Kiszka <[email protected]>
Date: 2017-09-05 (Tue, 05 Sep 2017)
Changed paths:
M hypervisor/arch/arm/control.c
M hypervisor/arch/arm/gic-v3.c
M hypervisor/arch/arm/include/asm/cell.h
Log Message:
-----------
arm: Declare each redistributor region to be last
As long as we are virtualizing MPIDR and, thus, also the region layout,
we can easily mark the end. However, when removing this virtualization
and starting to hand out the regions as-is, it will become complex to
identify contiguous ones.
To make this simple (for the hypervisor), just declare each of them to
be last. That means we will have to construct device trees for non-root
cells that declare multiple redistributor regions, even if they are
physically contiguous.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 5db9788ff2c81c8e3ba7eeba5e83a9608b0e6456
https://github.com/siemens/jailhouse/commit/5db9788ff2c81c8e3ba7eeba5e83a9608b0e6456
Author: Jan Kiszka <[email protected]>
Date: 2017-09-05 (Tue, 05 Sep 2017)
Changed paths:
M hypervisor/arch/arm/gic-v3.c
Log Message:
-----------
arm: Switch redistributor handling completely to MMIO dispatcher
We can avoid the extra loop in gic_handle_redist_access just to map the
virtual GICR address to its corresponding CPU. We just need to register
one redist region per cell CPU.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 1999e53c58891cffe2c6fd5619e003ba423098c4
https://github.com/siemens/jailhouse/commit/1999e53c58891cffe2c6fd5619e003ba423098c4
Author: Jan Kiszka <[email protected]>
Date: 2017-09-05 (Tue, 05 Sep 2017)
Changed paths:
M hypervisor/arch/arm/gic-v3.c
M hypervisor/arch/arm/include/asm/sysregs.h
Log Message:
-----------
arm: Detect unsupported Aff0 values in MPIDR
Just to be safe: ICC_SGI1R_EL1 allows us to address at most 16 cores in
the most significant affinity level. Encode this restriction in the init
code because we will rely on it during runtime.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: ecb878bb80a188613e0655f3e99399e50f405511
https://github.com/siemens/jailhouse/commit/ecb878bb80a188613e0655f3e99399e50f405511
Author: Jan Kiszka <[email protected]>
Date: 2017-09-05 (Tue, 05 Sep 2017)
Changed paths:
M hypervisor/arch/arm/gic-v3.c
M hypervisor/arch/arm/include/asm/percpu.h
M hypervisor/arch/arm64/include/asm/percpu.h
Log Message:
-----------
arm, arm64: Move gicr per-cpu parameter into struct
This prepares for adding another GICv3 parameter later on.
ARM64 is not using the field yet, but it already carries it. So update
this side as well.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 1f8090d277f04350eb11b197a52a6cbfa8bc74a3
https://github.com/siemens/jailhouse/commit/1f8090d277f04350eb11b197a52a6cbfa8bc74a3
Author: Jan Kiszka <[email protected]>
Date: 2017-09-05 (Tue, 05 Sep 2017)
Changed paths:
M hypervisor/arch/arm/gic-v3.c
M hypervisor/arch/arm/include/asm/percpu.h
M hypervisor/arch/arm64/include/asm/percpu.h
Log Message:
-----------
arm, arm64: Track physical address of redistributors for each CPU
We will need this once we start to identity-map the redistributors. And
while we could currently still calculate the addresses, better prepare
for multiple redist regions and store the address along the mapping.
Again, the update on ARM64 is just to prepare for eventually sharing the
GICv3.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: d1afff4d86ab425a3102542f87378b544fd5a1ae
https://github.com/siemens/jailhouse/commit/d1afff4d86ab425a3102542f87378b544fd5a1ae
Author: Jan Kiszka <[email protected]>
Date: 2017-09-05 (Tue, 05 Sep 2017)
Changed paths:
M configs/dts/inmate-bananapi.dts
M configs/dts/inmate-jetson-tk1.dts
M configs/dts/inmate-orangepi0.dts
M hypervisor/arch/arm-common/include/asm/gic.h
M hypervisor/arch/arm-common/irqchip.c
M hypervisor/arch/arm/control.c
M hypervisor/arch/arm/gic-v3.c
M hypervisor/arch/arm/include/asm/sysregs.h
M hypervisor/arch/arm64/include/asm/sysregs.h
Log Message:
-----------
arm: Remove MPIDR virtualization
Do not modify the MPIDR value that the cells see. VMPIDR is initialized
to the physical MPIDR on reset, and we can safely keep this, even while
the GICv2 IDs are still virtualized because they are unrelated.
We just need to adjust the GICv3 case because there we are in affinity
routing mode, and the MPIDR does play a role when dispatching SGIs.
GICR_TYPER can now be kept almost unmodified. Moreover, the
redistributors needs to be identity-mapped into the guests.
This also aligns arm with arm64 and will help introducing GICv3 to the
latter.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 9352c5cc723c73e0657f2d36cd963af53904dfd0
https://github.com/siemens/jailhouse/commit/9352c5cc723c73e0657f2d36cd963af53904dfd0
Author: Jan Kiszka <[email protected]>
Date: 2017-09-05 (Tue, 05 Sep 2017)
Changed paths:
M hypervisor/arch/arm-common/irqchip.c
M hypervisor/arch/arm/control.c
M hypervisor/arch/arm/include/asm/percpu.h
M hypervisor/arch/arm/setup.c
M hypervisor/arch/arm64/control.c
M hypervisor/arch/arm64/include/asm/percpu.h
Log Message:
-----------
arm, arm64: Remove remaining traces of virt_id
No more users of arm_cpu_phys2virt/virt2phys are remaining, so we can
purge the code from related fragments.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 3f37663456c66ee4a7898c3b93c28deb9b578bce
https://github.com/siemens/jailhouse/commit/3f37663456c66ee4a7898c3b93c28deb9b578bce
Author: Lokesh Vutla <[email protected]>
Date: 2017-09-06 (Wed, 06 Sep 2017)
Changed paths:
M hypervisor/arch/arm/gic-v3.c
Log Message:
-----------
arm: gicv3: Fix the GICD_IROUTER offset
Commit 61e30277199e5 ("GICv3: Fix the GICD_IROUTER offset")
in ATF[1] specifies that GICv3 documention mentions the wrong offset
about GICD_IROUTER and gives proper calculation for interrupt id.
Importing the same here.
[1] https://github.com/ARM-software/arm-trusted-firmware
Signed-off-by: Lokesh Vutla <[email protected]>
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 22a3e833046d24247cdfb46189dbe5bf4ea5a78f
https://github.com/siemens/jailhouse/commit/22a3e833046d24247cdfb46189dbe5bf4ea5a78f
Author: Lokesh Vutla <[email protected]>
Date: 2017-09-06 (Wed, 06 Sep 2017)
Changed paths:
M hypervisor/arch/arm/gic-v3.c
M hypervisor/arch/arm/include/asm/sysregs.h
M hypervisor/arch/arm64/include/asm/sysregs.h
Log Message:
-----------
arm: gicv3: Fix detection of redistributor
MPIDR can be used to compare the GICR_TYPER register
for redistributor base calculation. Logic is imported from
kernel.
Signed-off-by: Lokesh Vutla <[email protected]>
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 6249d46fb7a85ef1712a5ef0102d212c65b5bc46
https://github.com/siemens/jailhouse/commit/6249d46fb7a85ef1712a5ef0102d212c65b5bc46
Author: Lokesh Vutla <[email protected]>
Date: 2017-09-06 (Wed, 06 Sep 2017)
Changed paths:
M hypervisor/arch/arm/gic-v3.c
Log Message:
-----------
arm: gicv3: Fix irq target adjustments by using MPIDR
cpu_id (returned by first_cpu) may not match aff0 in mpidr. Fix this by
always using affinity values in GICD_IROUTER. This also prepares for
clusters.
Signed-off-by: Lokesh Vutla <[email protected]>
[Jan: massage log message]
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 6b92e0ea5326b193f9652c9f15ee94a749d707b0
https://github.com/siemens/jailhouse/commit/6b92e0ea5326b193f9652c9f15ee94a749d707b0
Author: Lokesh Vutla <[email protected]>
Date: 2017-09-06 (Wed, 06 Sep 2017)
Changed paths:
M hypervisor/arch/arm-common/include/asm/irqchip.h
M hypervisor/arch/arm-common/irqchip.c
M hypervisor/arch/arm/gic-v3.c
Log Message:
-----------
arm-common: Use cluster_id instead of affinity levels
For simplicity pass cluster id derived from mpidr instead of
passing affinity levels separately.
Signed-off-by: Lokesh Vutla <[email protected]>
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 90f6931ba05c58de366b93020e7f200a805889d1
https://github.com/siemens/jailhouse/commit/90f6931ba05c58de366b93020e7f200a805889d1
Author: Ralf Ramsauer <[email protected]>
Date: 2017-09-06 (Wed, 06 Sep 2017)
Changed paths:
M hypervisor/Makefile
M hypervisor/arch/arm-common/Kbuild
M inmates/lib/arm/Makefile.lib
M inmates/lib/arm64/Makefile.lib
Log Message:
-----------
core, inmates: optionally include config.mk in Makefiles
Otherwise successive cleans, like
make clean; make clean
will fail.
Signed-off-by: Ralf Ramsauer <[email protected]>
Signed-off-by: Jan Kiszka <[email protected]>
Compare:
https://github.com/siemens/jailhouse/compare/61f738d2740b...90f6931ba05c
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