On 2017-07-20 11:19, 'Nikhil Devshatwar' via Jailhouse wrote:
> Getting compiler issues when using GIC V3 in 64bit mode
> Update the sysreg macros to solve these compiler issues
> 
> Signed-off-by: Nikhil Devshatwar <[email protected]>
> ---
>  hypervisor/arch/arm-common/include/asm/gic_v3.h |  2 +-
>  hypervisor/arch/arm64/include/asm/sysregs.h     | 12 +++++++++---
>  2 files changed, 10 insertions(+), 4 deletions(-)
> 
> diff --git a/hypervisor/arch/arm-common/include/asm/gic_v3.h 
> b/hypervisor/arch/arm-common/include/asm/gic_v3.h
> index d1b9346..1fcd5a4 100644
> --- a/hypervisor/arch/arm-common/include/asm/gic_v3.h
> +++ b/hypervisor/arch/arm-common/include/asm/gic_v3.h
> @@ -70,7 +70,7 @@
>  #define ICC_SRE_EL1          SYSREG_32(0, c12, c12, 5)
>  #define ICC_SRE_EL2          SYSREG_32(4, c12, c9, 5)
>  #define ICC_IGRPEN1_EL1              SYSREG_32(0, c12, c12, 7)
> -#define ICC_SGI1R_EL1                SYSREG_64(0, c12)
> +#define ICC_SGI1R_EL1                SYSREG_64(0, c12, c11, 5)

This one is differently defined for ARM vs. ARM64. You need to account
for that.

Jan

>  #define ICC_AP1R0_EL1                SYSREG_32(0, c12, c9, 0)
>  #define ICC_AP1R1_EL1                SYSREG_32(0, c12, c9, 1)
>  #define ICC_AP1R2_EL1                SYSREG_32(0, c12, c9, 2)
> diff --git a/hypervisor/arch/arm64/include/asm/sysregs.h 
> b/hypervisor/arch/arm64/include/asm/sysregs.h
> index d0f8fa3..565012b 100644
> --- a/hypervisor/arch/arm64/include/asm/sysregs.h
> +++ b/hypervisor/arch/arm64/include/asm/sysregs.h
> @@ -146,11 +146,17 @@
>  
>  #ifndef __ASSEMBLY__
>  
> -#define arm_write_sysreg(sysreg, val) \
> +#define SYSREG_32(a, b, c, d)  s3_##a ##_##b ##_##c ##_##d
> +#define SYSREG_64(a, b, c, d)        s3_##a ##_##b ##_##c ##_##d
> +
> +
> +#define arm_write_sysreg1(sysreg, val) \
>       asm volatile ("msr      "#sysreg", %0\n" : : "r"((u64)(val)))
> +#define arm_write_sysreg(a , b) arm_write_sysreg1( a, b)
>  
> -#define arm_read_sysreg(sysreg, val) \
> -     asm volatile ("mrs      %0, "#sysreg"\n" : "=r"((u64)(val)))
> +#define arm_read_sysreg1(sysreg, val) \
> +     asm volatile ("mrs      %0,  "#sysreg"\n" : "=r"((val)))
> +#define arm_read_sysreg(a , b) arm_read_sysreg1( a, b)
>  
>  #endif /* __ASSEMBLY__ */
>  
> 

-- 
Siemens AG, Corporate Technology, CT RDA ITP SES-DE
Corporate Competence Center Embedded Linux

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