Hi,

just realised that this patch breaks my inmate-decouple series after
rebasing it to next.

Reason for that is that gic-v3 is now available for ARM64, and my
decouple series misses SYSREG_32 definition for that architecture, as I
only provided a minimum set of definitions. In addition to that, I also
need strings.h, as sysregs.h now uses __stringify. Maybe I can get
around that somehow...

As Tony didn't give his signed-off yet, I'll provide a new patch for that.

  Ralf

On 23/07/17 11:59, Jan Kiszka wrote:
> Here you could state that all register accesses are valid for both arm
> and arm64 - provided you checked that they are.
> 
> Jan
> 
> On 2017-07-20 11:19, 'Nikhil Devshatwar' via Jailhouse wrote:
>> Signed-off-by: Nikhil Devshatwar <[email protected]>
>> ---
>>  inmates/lib/arm-common/Makefile.lib |  1 +
>>  inmates/lib/arm-common/gic-v3.c     | 58 
>> +++++++++++++++++++++++++++++++++++++
>>  inmates/lib/arm/Makefile            |  1 -
>>  inmates/lib/arm/gic-v3.c            | 58 
>> -------------------------------------
>>  4 files changed, 59 insertions(+), 59 deletions(-)
>>  create mode 100644 inmates/lib/arm-common/gic-v3.c
>>  delete mode 100644 inmates/lib/arm/gic-v3.c
>>
>> diff --git a/inmates/lib/arm-common/Makefile.lib 
>> b/inmates/lib/arm-common/Makefile.lib
>> index f66f452..31c0855 100644
>> --- a/inmates/lib/arm-common/Makefile.lib
>> +++ b/inmates/lib/arm-common/Makefile.lib
>> @@ -16,5 +16,6 @@ OBJS-y := ../string.o ../cmdline.o
>>  OBJS-y += printk.o gic.o timer.o
>>  OBJS-y += uart-jailhouse.o uart-pl011.o uart-8250.o uart-xuartps.o
>>  OBJS-$(CONFIG_ARM_GIC_V2) += gic-v2.o
>> +OBJS-$(CONFIG_ARM_GIC_V3) += gic-v3.o
>>  
>>  COMMON_OBJECTS = $(addprefix ../arm-common/,$(OBJS-y))
>> diff --git a/inmates/lib/arm-common/gic-v3.c 
>> b/inmates/lib/arm-common/gic-v3.c
>> new file mode 100644
>> index 0000000..6831597
>> --- /dev/null
>> +++ b/inmates/lib/arm-common/gic-v3.c
>> @@ -0,0 +1,58 @@
>> +/*
>> + * Jailhouse, a Linux-based partitioning hypervisor
>> + *
>> + * Copyright (c) ARM Limited, 2014
>> + *
>> + * Authors:
>> + *  Jean-Philippe Brucker <[email protected]>
>> + *
>> + * This work is licensed under the terms of the GNU GPL, version 2.  See
>> + * the COPYING file in the top-level directory.
>> + */
>> +
>> +#include <asm/sysregs.h>
>> +#include <mach.h>
>> +#include <gic.h>
>> +
>> +#define GICR_SGI_BASE               0x10000
>> +#define GICR_ISENABLER              GICD_ISENABLER
>> +
>> +#define ICC_IAR1_EL1                SYSREG_32(0, c12, c12, 0)
>> +#define ICC_EOIR1_EL1               SYSREG_32(0, c12, c12, 1)
>> +#define ICC_PMR_EL1         SYSREG_32(0, c4, c6, 0)
>> +#define ICC_CTLR_EL1                SYSREG_32(0, c12, c12, 4)
>> +#define ICC_IGRPEN1_EL1             SYSREG_32(0, c12, c12, 7)
>> +
>> +#define ICC_IGRPEN1_EN              0x1
>> +
>> +void gic_enable(unsigned int irqn)
>> +{
>> +    if (is_sgi_ppi(irqn))
>> +            mmio_write32(GICR_V3_BASE + GICR_SGI_BASE + GICR_ISENABLER,
>> +                         1 << irqn);
>> +    else if (is_spi(irqn))
>> +            mmio_write32(GICD_V3_BASE + GICD_ISENABLER + irqn / 32,
>> +                         1 << (irqn % 32));
>> +}
>> +
>> +int gic_init(void)
>> +{
>> +    arm_write_sysreg(ICC_CTLR_EL1, 0);
>> +    arm_write_sysreg(ICC_PMR_EL1, 0xf0);
>> +    arm_write_sysreg(ICC_IGRPEN1_EL1, ICC_IGRPEN1_EN);
>> +
>> +    return 0;
>> +}
>> +
>> +void gic_write_eoi(u32 irqn)
>> +{
>> +    arm_write_sysreg(ICC_EOIR1_EL1, irqn);
>> +}
>> +
>> +u32 gic_read_ack(void)
>> +{
>> +    u32 val;
>> +
>> +    arm_read_sysreg(ICC_IAR1_EL1, val);
>> +    return val;
>> +}
>> diff --git a/inmates/lib/arm/Makefile b/inmates/lib/arm/Makefile
>> index 7326c32..bc17e07 100644
>> --- a/inmates/lib/arm/Makefile
>> +++ b/inmates/lib/arm/Makefile
>> @@ -19,4 +19,3 @@ ccflags-y := -ffunction-sections
>>  
>>  lib-y                               := $(COMMON_OBJECTS)
>>  lib-y                               += header.o
>> -lib-$(CONFIG_ARM_GIC_V3)    += gic-v3.o
>> diff --git a/inmates/lib/arm/gic-v3.c b/inmates/lib/arm/gic-v3.c
>> deleted file mode 100644
>> index 6831597..0000000
>> --- a/inmates/lib/arm/gic-v3.c
>> +++ /dev/null
>> @@ -1,58 +0,0 @@
>> -/*
>> - * Jailhouse, a Linux-based partitioning hypervisor
>> - *
>> - * Copyright (c) ARM Limited, 2014
>> - *
>> - * Authors:
>> - *  Jean-Philippe Brucker <[email protected]>
>> - *
>> - * This work is licensed under the terms of the GNU GPL, version 2.  See
>> - * the COPYING file in the top-level directory.
>> - */
>> -
>> -#include <asm/sysregs.h>
>> -#include <mach.h>
>> -#include <gic.h>
>> -
>> -#define GICR_SGI_BASE               0x10000
>> -#define GICR_ISENABLER              GICD_ISENABLER
>> -
>> -#define ICC_IAR1_EL1                SYSREG_32(0, c12, c12, 0)
>> -#define ICC_EOIR1_EL1               SYSREG_32(0, c12, c12, 1)
>> -#define ICC_PMR_EL1         SYSREG_32(0, c4, c6, 0)
>> -#define ICC_CTLR_EL1                SYSREG_32(0, c12, c12, 4)
>> -#define ICC_IGRPEN1_EL1             SYSREG_32(0, c12, c12, 7)
>> -
>> -#define ICC_IGRPEN1_EN              0x1
>> -
>> -void gic_enable(unsigned int irqn)
>> -{
>> -    if (is_sgi_ppi(irqn))
>> -            mmio_write32(GICR_V3_BASE + GICR_SGI_BASE + GICR_ISENABLER,
>> -                         1 << irqn);
>> -    else if (is_spi(irqn))
>> -            mmio_write32(GICD_V3_BASE + GICD_ISENABLER + irqn / 32,
>> -                         1 << (irqn % 32));
>> -}
>> -
>> -int gic_init(void)
>> -{
>> -    arm_write_sysreg(ICC_CTLR_EL1, 0);
>> -    arm_write_sysreg(ICC_PMR_EL1, 0xf0);
>> -    arm_write_sysreg(ICC_IGRPEN1_EL1, ICC_IGRPEN1_EN);
>> -
>> -    return 0;
>> -}
>> -
>> -void gic_write_eoi(u32 irqn)
>> -{
>> -    arm_write_sysreg(ICC_EOIR1_EL1, irqn);
>> -}
>> -
>> -u32 gic_read_ack(void)
>> -{
>> -    u32 val;
>> -
>> -    arm_read_sysreg(ICC_IAR1_EL1, val);
>> -    return val;
>> -}
>>
> 

-- 
You received this message because you are subscribed to the Google Groups 
"Jailhouse" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to [email protected].
For more options, visit https://groups.google.com/d/optout.

Reply via email to