From: Otavio Pontes <otavio.pon...@intel.com>
If one has CONFIG_PCIEAER=y enabled in Linux inmates, from
pci_device_add() -> pci_init_capabilities() -> pci_aer_init() ->
pci_cleanup_aer_error_status_regs(), there *will* be writes to the AER
capability in it and, as it is now, Jailhouse will park the cell right
away. This commit makes the capability size guessed right and makes it
read/writable.
Also, the cell config creation tool was changed to allow writes to the
PCIe capability, while Jailhouse will in fact only do reads and fake
that writes happen. This is getting in so that Linux thinks it did OK at
pci_disable_pcie_error_reporting() (disabling AER reporting for
functions will be taken care of at hypervisor level on following
patches). That is a common function call from .remove() struct
pci_driver entries on drivers. The register that is accessed there is
Device Control (offset 08h) or its bits enabling/disabling AER reporting
on a device.
Signed-off-by: Otavio Pontes <otavio.pon...@intel.com>
Signed-off-by: Gustavo Lima Chaves <gustavo.lima.cha...@intel.com>
---
tools/jailhouse-config-create | 15 +++++++++++++--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/tools/jailhouse-config-create b/tools/jailhouse-config-create
index ce2affce..747efd42 100755
--- a/tools/jailhouse-config-create
+++ b/tools/jailhouse-config-create
@@ -226,6 +226,7 @@ class PCICapability:
def parse_pcicaps(dir):
caps = []
has_extended_caps = False
+ tlp_prefix_supported = False
f = input_open(os.path.join(dir, 'config'), 'rb')
f.seek(0x06)
(status,) = struct.unpack('<H', f.read(2))
@@ -259,8 +260,11 @@ class PCICapability:
(cap_reg,) = struct.unpack('<H', f.read(2))
if (cap_reg & 0xf) >= 2: # v2 capability
len = 60
- # access side effects still need to be analyzed
- flags = PCICapability.RD
+ # Let guests think they did OK when writing to this
+ # capability. The register of interest in writes there
+ # is Device Control, but it affects things that
+ # Jailhouse will take care of at hypervisor level.
+ flags = PCICapability.RW
has_extended_caps = True
elif id == 0x11: # MSI-X
# access will be moderated by hypervisor
@@ -297,6 +301,13 @@ class PCICapability:
len = 64
# access side effects still need to be analyzed
flags = PCICapability.RD
+ elif id == 0x0001: # AER
+ if tlp_prefix_supported:
+ len = 0x48
+ else:
+ len = 0x38
+ # AER access is per-function
+ flags = PCICapability.RW
else:
if (id & PCICapability.JAILHOUSE_PCI_EXT_CAP) != 0:
print('WARNING: Ignoring unsupported PCI Express '
--
2.14.3
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