[...]
* Jan Kiszka <[email protected]> [2018-01-20 12:09:32 +0100]:
> > + flags = PCICapability.RW
> > has_extended_caps = True
> > elif id == 0x11: # MSI-X
> > # access will be moderated by hypervisor
> > @@ -297,6 +301,13 @@ class PCICapability:
> > len = 64
> > # access side effects still need to be analyzed
> > flags = PCICapability.RD
> > + elif id == 0x0001: # AER
> > + if tlp_prefix_supported:
> > + len = 0x48
> > + else:
> > + len = 0x38
> > + # AER access is per-function
>
> ...and reporting is disabled by Jailhouse at bridge-level, right? Please
> leave a remark about that as well.
Yes, will do.
>
> > + flags = PCICapability.RW
> > else:
> > if (id & PCICapability.JAILHOUSE_PCI_EXT_CAP) != 0:
> > print('WARNING: Ignoring unsupported PCI Express '
> >
>
> As stated in an earlier patch, we need some reasonable default value for
> pci_flr_timeout. So please also update the config template and existing
> x86 configs. Otherwise, they will fail while trying to reset some function.
Fair.
>
> Jan
>
> --
> Siemens AG, Corporate Technology, CT RDA IOT SES-DE
> Corporate Competence Center Embedded Linux
--
Gustavo Lima Chaves
Intel - Open Source Technology Center
--
You received this message because you are subscribed to the Google Groups
"Jailhouse" group.
To unsubscribe from this group and stop receiving emails from it, send an email
to [email protected].
For more options, visit https://groups.google.com/d/optout.
