From: Jan Kiszka <jan.kis...@siemens.com> Makes the mask more readable. There is also no need for a separate define because only HSR/ESR_ISS makes use of it.
Signed-off-by: Jan Kiszka <jan.kis...@siemens.com> --- hypervisor/arch/arm/include/asm/sysregs.h | 3 +-- hypervisor/arch/arm64/include/asm/sysregs.h | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/hypervisor/arch/arm/include/asm/sysregs.h b/hypervisor/arch/arm/include/asm/sysregs.h index afcb45ec..6c9a53c5 100644 --- a/hypervisor/arch/arm/include/asm/sysregs.h +++ b/hypervisor/arch/arm/include/asm/sysregs.h @@ -113,8 +113,7 @@ #define HSR_IL_SHIFT 25 #define HSR_IL(hsr) ((hsr) >> HSR_IL_SHIFT & 0x1) /* Instruction specific */ -#define HSR_ISS_MASK 0x1ffffff -#define HSR_ISS(hsr) ((hsr) & HSR_ISS_MASK) +#define HSR_ISS(hsr) ((hsr) & BIT_MASK(24, 0)) /* Exception classes values */ #define HSR_EC_UNK 0x00 #define HSR_EC_WFI 0x01 diff --git a/hypervisor/arch/arm64/include/asm/sysregs.h b/hypervisor/arch/arm64/include/asm/sysregs.h index 742434d0..d3feee0f 100644 --- a/hypervisor/arch/arm64/include/asm/sysregs.h +++ b/hypervisor/arch/arm64/include/asm/sysregs.h @@ -113,8 +113,7 @@ #define ESR_IL_SHIFT 25 #define ESR_IL(hsr) ((hsr) >> ESR_IL_SHIFT & 0x1) /* Instruction specific syndrom */ -#define ESR_ISS_MASK 0x1ffffff -#define ESR_ISS(esr) ((esr) & ESR_ISS_MASK) +#define ESR_ISS(esr) ((esr) & BIT_MASK(24, 0)) /* Exception classes values */ #define ESR_EC_UNKNOWN 0x00 #define ESR_EC_WFx 0x01 -- 2.13.6 -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to jailhouse-dev+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
