From: Jan Kiszka <[email protected]> It's called ISS according to the ARM manual, not ICC.
No functional changes. Signed-off-by: Jan Kiszka <[email protected]> --- hypervisor/arch/arm/include/asm/sysregs.h | 8 ++++---- hypervisor/arch/arm/mmio.c | 18 +++++++++--------- hypervisor/arch/arm/traps.c | 6 +++--- 3 files changed, 16 insertions(+), 16 deletions(-) diff --git a/hypervisor/arch/arm/include/asm/sysregs.h b/hypervisor/arch/arm/include/asm/sysregs.h index 797585b4..afcb45ec 100644 --- a/hypervisor/arch/arm/include/asm/sysregs.h +++ b/hypervisor/arch/arm/include/asm/sysregs.h @@ -113,8 +113,8 @@ #define HSR_IL_SHIFT 25 #define HSR_IL(hsr) ((hsr) >> HSR_IL_SHIFT & 0x1) /* Instruction specific */ -#define HSR_ICC_MASK 0x1ffffff -#define HSR_ICC(hsr) ((hsr) & HSR_ICC_MASK) +#define HSR_ISS_MASK 0x1ffffff +#define HSR_ISS(hsr) ((hsr) & HSR_ISS_MASK) /* Exception classes values */ #define HSR_EC_UNK 0x00 #define HSR_EC_WFI 0x01 @@ -134,8 +134,8 @@ #define HSR_EC_DABT 0x24 #define HSR_EC_DABT_HYP 0x25 /* Condition code */ -#define HSR_ICC_CV_BIT (1 << 24) -#define HSR_ICC_COND(icc) ((icc) >> 20 & 0xf) +#define HSR_ISS_CV_BIT (1 << 24) +#define HSR_ISS_COND(iss) ((iss) >> 20 & 0xf) #define HSR_MATCH_MCR_MRC(hsr, crn, opc1, crm, opc2) \ (((hsr) & (BIT_MASK(19, 10) | BIT_MASK(4, 1))) == \ diff --git a/hypervisor/arch/arm/mmio.c b/hypervisor/arch/arm/mmio.c index b3f76696..25e4b52a 100644 --- a/hypervisor/arch/arm/mmio.c +++ b/hypervisor/arch/arm/mmio.c @@ -76,15 +76,15 @@ int arch_handle_dabt(struct trap_context *ctx) unsigned long hpfar; unsigned long hdfar; /* Decode the syndrome fields */ - u32 icc = HSR_ICC(ctx->hsr); - u32 isv = icc >> 24; - u32 sas = icc >> 22 & 0x3; - u32 sse = icc >> 21 & 0x1; - u32 srt = icc >> 16 & 0xf; - u32 ea = icc >> 9 & 0x1; - u32 cm = icc >> 8 & 0x1; - u32 s1ptw = icc >> 7 & 0x1; - u32 is_write = icc >> 6 & 0x1; + u32 iss = HSR_ISS(ctx->hsr); + u32 isv = iss >> 24; + u32 sas = iss >> 22 & 0x3; + u32 sse = iss >> 21 & 0x1; + u32 srt = iss >> 16 & 0xf; + u32 ea = iss >> 9 & 0x1; + u32 cm = iss >> 8 & 0x1; + u32 s1ptw = iss >> 7 & 0x1; + u32 is_write = iss >> 6 & 0x1; u32 size = 1 << sas; arm_read_sysreg(HPFAR, hpfar); diff --git a/hypervisor/arch/arm/traps.c b/hypervisor/arch/arm/traps.c index cf27ec09..f75a3b00 100644 --- a/hypervisor/arch/arm/traps.c +++ b/hypervisor/arch/arm/traps.c @@ -51,7 +51,7 @@ static const unsigned short cc_map[16] = { static bool arch_failed_condition(struct trap_context *ctx) { u32 class = HSR_EC(ctx->hsr); - u32 icc = HSR_ICC(ctx->hsr); + u32 iss = HSR_ISS(ctx->hsr); u32 cpsr, flags, cond; arm_read_banked_reg(SPSR_hyp, cpsr); @@ -65,8 +65,8 @@ static bool arch_failed_condition(struct trap_context *ctx) return false; /* Is condition field valid? */ - if (icc & HSR_ICC_CV_BIT) { - cond = HSR_ICC_COND(icc); + if (iss & HSR_ISS_CV_BIT) { + cond = HSR_ISS_COND(iss); } else { /* This can happen in Thumb mode: examine IT state. */ unsigned long it = PSR_IT(cpsr); -- 2.13.6 -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
