Hello,
I would like to share buffers among cells on arm64 (Xilinx ultrascale+). The
documentation suggests the use of the ivshmem.
In order to use ivshmem, I changed the root cell config as follows (it is based
on the zynqmp-zcu102.c original file):
- In the .mem_regions:
/* IVSHMEM shared memory region for 00:00.0 */ {
.phys_start = 0x800400000,
.virt_start = 0x800400000,
.size = 0x100000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_ROOTSHARED, //added JAILHOUSE_MEM_ROOTSHARED
},
- In the .pci_devices:
/* 00:00.0 */ {
.type = JAILHOUSE_PCI_TYPE_IVSHMEM,
.bdf = 0 << 3,
.bar_mask = {
0xffffff00, 0xffffffff, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.shmem_region = 3,
.shmem_protocol = JAILHOUSE_SHMEM_PROTO_VETH,
.num_msix_vectors = 1,
.iommu = 1,
},
Then, I load the cell:
jailhouse enable zynqmp-zcu102-ivshmem.cell
Initializing Jailhouse hypervisor v0.8 (37-g1fa9001) on CPU 1
Code location: 0x0000ffffc0200060
Page pool usage after early setup: mem 33/995, remap 64/131072
Initializing processors:
CPU 1... OK
CPU 2... OK
CPU 0... OK
CPU 3... OK
Adding virtual PCI device 00:00.0 to cell "ZynqMP-ZCU102"
Adding virtual PCI device 00:01.0 to cell "ZynqMP-ZCU102"
Page pool usage after late setup: mem 42/995, remap 69/131072
Activating hypervisor
Then, I wrote a simple user-space program that maps the virtual PCI ivshmem
region to user using mmap:
memfd = open("/dev/mem", O_RDWR | O_SYNC);
mapped_base = mmap(0, MEM_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, memfd,
0xfc100000 & ~MEM_MASK);
mapped_dev_base = mapped_base + (dev_base & MEM_MASK);
for(int i = 0; i < 8; i += 4) {
*((volatile unsigned int *) (mapped_dev_base + i)) = 1;
printf("Address: %p, Read valeu = %d\n", (void *)(mapped_dev_base + i),
*((unsigned int *) (mapped_dev_base + i)));
}
When I ran this program in the root cell, I got the following Unhandled trap:
./ivshmem_test
/dev/mem opened.
Memory mapped at address 0x7f8dd87000.
Unhandled data write at 0xfc100000(4)
FATAL: unhandled trap (exception class 0x24)
Cell state before exception:
pc: 0000000000400904 lr: 00000000004008d8 spsr: 80000000 EL0
sp: 0000007fceff8df0 esr: 24 1 1810046
x0: 0000007f8dd87000 x1: 0000000000000001 x2: 0000000000000001
x3: 0000000000000000 x4: 0000000040100401 x5: 5404000000000000
x6: 000000001aec1037 x7: 0000000000000000 x8: 0000000000000040
x9: ffffff80ffffffc8 x10: 0000007fceff8df0 x11: 0000007fceff8df0
x12: 00000000000003f3 x13: 0000000000000000 x14: 0000000000000000
x15: 0000007f8dd8ecc0 x16: 0000000000000000 x17: 0000007f8dc53240
x18: 0000000000000a03 x19: 00000000004009a8 x20: 0000000000000000
x21: 0000000000000000 x22: 0000000000000000 x23: 0000000000000000
x24: 0000000000000000 x25: 0000000000000000 x26: 0000000000000000
x27: 0000000000000000 x28: 0000000000000000 x29: 0000007fceff8df0
Parking CPU 2 (Cell: "ZynqMP-ZCU102")
Does that make sense? Am I missing something in the root cell config or the
user-space program is wrong?
Best regards
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