Il giorno giovedì 12 aprile 2018 08:51:39 UTC+2, Claudio Scordino ha scritto:
> Hi Giovani,
>
>
>
>
> 2018-04-12 8:01 GMT+02:00 Jan Kiszka <jan.k...@siemens.com>:
> On 2018-04-11 19:40, Giovani Gracioli wrote:
>
> > Here is the output of the unhandled data read:
>
> >
>
> > Unhandled data read at 0xfc100000(2)
>
> >
>
> > FATAL: unhandled trap (exception class 0x24)
>
> > Cell state before exception:
>
> > pc: 0000000000001828 lr: 00000000000015f0 spsr: 60000005 EL1
>
> > sp: 0000000000003f30 esr: 24 1 1400006
>
> > x0: 00000000fc100000 x1: 0000000000000000 x2: 0000000000000002
>
> > x3: 00000000fc000000 x4: 0000000000000000 x5: 0000000000000000
>
> > x6: 0000000000001000 x7: 0000000000000000 x8: 0000000000000000
>
> > x9: 0000000000000000 x10: 0000000000000000 x11: 0000000000000000
>
> > x12: 0000000000000000 x13: 0000000000000000 x14: 0000000000000000
>
> > x15: 0000000000000000 x16: 0000000000000000 x17: 0000000000000000
>
> > x18: 0000000000000000 x19: 0000000000001000 x20: 000000000000ffff
>
> > x21: 0000000000001af4 x22: 0000000000001110 x23: 0000000000001000
>
> > x24: 0000000000002660 x25: 0000000000000000 x26: 0000000000000000
>
> > x27: 0000000000000000 x28: 0000000000000000 x29: 0000000000000000
>
> >
>
> > Parking CPU 3 (Cell: "gic-demo-ivshmem")
>
> >
>
> > Am I missing something in the configuration?
>
>
>
> Possibly. As this is code of Claudio and his colleagues, he may answer
>
> this better.
>
>
>
> A collegue of mine is looking at your issue.
>
>
> BTW, we plan to have a version of the PCI stuff rebased upstream in a couple
> of weeks.
>
> We'll post it on the ML once ready.
>
>
> Regards,
>
>
> Claudio
Hi all,
i'm trying to understand what's wrong in the configuration.
1. The PCI configuration of the root cell (and its relative shared memory
region ) needs a counterpart in the inmate configuration. The two PCI must have
the same bdf. In fact when the configuration is ok, jailhouse prints on the
screen che binding between the PCI devices.
2. The starting search address of the inmate library (#define PCI_CFG_BASE in
inmates/lib/arm-common/pci.c) must be the same of the platform_info section in
the root cell configuration (
.platform_info = {
.pci_mmconfig_base = 0x48000000,
.pci_mmconfig_end_bus = 0x0,
.pci_is_virtual = 1,
.....
)
3. The best way to access the shared memory region from linux is using the
uio_ivshmem driver. It works correctly on ARM64. It just needs the UIO kernel
module as dependency. Once loaded, you can see memory infos in
/sys/class/uio/uio0/maps[0,1] which are shmem informations and bar information.
Regards,
--Luca
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