Hi, The configs are attached. I am running Erika on the non-root cell.
> > Don't know exactly why, but if I change the size for 1MB instead of 2MB, it > > works. > > > > Is this because of this line in the mmu_cell.c? > > > > size = MIN(region_size, NUM_TEMPORARY_PAGES * PAGE_SIZE); > > > > Thus, is the maximum size of any memory region 1MB? > > > > No, the minimum size is 4K on all supported architectures. > > Without the configs you were using, it's hard to say where the mistake is. > > Also, what kind of inmate are you booting in the non-root cell? > > Jan > > >> Hi, > >> > >> I checked the array sizes and they are correct. num_memory_regions uses > >> the ARRAY_SIZE macro: > >> > >> .num_memory_regions = ARRAY_SIZE(config.mem_regions) > >> > >> In Linux I can mmap and access the mapped region without errors. > >> > >> Any other thought? > >> > >>> > >>> Maybe the region was not properly registered. Did you increase the > >>> mem_regions array size? Did you change num_memory_regions so that it > >>> requires manual updates? That's better discussed over the full config. > >>> > >>> Note that, if you want to share a region between root and non-root cell, > >>> the latter also needs JAILHOUSE_MEM_ROOTSHARED. > >>> > >>> Jan > > -- > Siemens AG, Corporate Technology, CT RDA IOT SES-DE > Corporate Competence Center Embedded Linux -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
/* * Jailhouse, a Linux-based partitioning hypervisor * * Configuration for Xilinx ZynqMP ZCU102 eval board * * Copyright (c) Siemens AG, 2016 * * Authors: * Jan Kiszka <[email protected]> * * This work is licensed under the terms of the GNU GPL, version 2. See * the COPYING file in the top-level directory. * * Reservation via device tree: 0x800000000..0x83fffffff */ #include <jailhouse/types.h> #include <jailhouse/cell-config.h> #define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0])) struct { struct jailhouse_system header; __u64 cpus[1]; struct jailhouse_memory mem_regions[7]; struct jailhouse_irqchip irqchips[1]; struct jailhouse_pci_device pci_devices[3]; } __attribute__((packed)) config = { .header = { .signature = JAILHOUSE_SYSTEM_SIGNATURE, .revision = JAILHOUSE_CONFIG_REVISION, .hypervisor_memory = { .phys_start = 0x800000000, .size = 0x000400000, }, .debug_console = { .address = 0xff000000, .size = 0x1000, .flags = JAILHOUSE_CON1_TYPE_XUARTPS | JAILHOUSE_CON1_ACCESS_MMIO | JAILHOUSE_CON1_REGDIST_4 | JAILHOUSE_CON2_TYPE_ROOTPAGE, }, .platform_info = { .pci_mmconfig_base = 0xfc000000, .pci_mmconfig_end_bus = 0, .pci_is_virtual = 1, .arm = { .gic_version = 2, .gicd_base = 0xf9010000, .gicc_base = 0xf902f000, .gich_base = 0xf9040000, .gicv_base = 0xf906f000, .maintenance_irq = 25, }, }, .root_cell = { .name = "ZynqMP-ZCU102", .cpu_set_size = sizeof(config.cpus), .num_memory_regions = ARRAY_SIZE(config.mem_regions), .num_irqchips = ARRAY_SIZE(config.irqchips), .num_pci_devices = ARRAY_SIZE(config.pci_devices), .vpci_irq_base = 136-32, }, }, .cpus = { 0xf, }, .mem_regions = { /* MMIO (permissive) */ { .phys_start = 0xfd000000, .virt_start = 0xfd000000, .size = 0x03000000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO, }, /* RAM */ { .phys_start = 0x0, .virt_start = 0x0, .size = 0x80000000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_EXECUTE, }, /* RAM */ { .phys_start = 0x800600000, .virt_start = 0x800600000, .size = 0x7fa00000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_EXECUTE, }, /* IVSHMEM shared memory region for 00:00.0 */ { .phys_start = 0x800400000, .virt_start = 0x800400000, .size = 0x100000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE, }, /* IVSHMEM shared memory region for 00:02.0 */ { .phys_start = 0x800800000, .virt_start = 0x800800000, .size = 0x100000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE, }, /* IVSHMEM shared memory region for 00:01.0 */ { .phys_start = 0x800700000, .virt_start = 0x800700000, .size = 0x100000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE, }, /* BRAM */ { .phys_start = 0x500000000, .virt_start = 0x500000000, .size = 0x100000, //1MB .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE, }, }, .irqchips = { /* GIC */ { .address = 0xf9010000, .pin_base = 32, .pin_bitmap = { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, }, }, }, .pci_devices = { /* 00:00.0 */ { .type = JAILHOUSE_PCI_TYPE_IVSHMEM, .bdf = 0, .bar_mask = { 0xffffff00, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, .shmem_region = 3, .shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED, .num_msix_vectors = 0, .domain = 0, }, /* 00:02.0 */ { .type = JAILHOUSE_PCI_TYPE_IVSHMEM, .bdf = 2 << 3, .bar_mask = { 0xfffff000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, .shmem_region = 4, .shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED, .num_msix_vectors = 0, .domain = 0, }, /* 00:01.0 */ { .type = JAILHOUSE_PCI_TYPE_IVSHMEM, .bdf = 1 << 3, .bar_mask = { 0xffff7000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, .shmem_region = 5, .shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED, .num_msix_vectors = 0, .domain = 0, }, }, };
/* * Jailhouse, a Linux-based partitioning hypervisor * * Configuration for gic-demo inmate on Xilinx ZynqMP ZCU102 eval board: * 1 CPU, 64K RAM, 1 serial port * * Copyright (c) Siemens AG, 2016 * * Authors: * Jan Kiszka <[email protected]> * * This work is licensed under the terms of the GNU GPL, version 2. See * the COPYING file in the top-level directory. */ #include <jailhouse/types.h> #include <jailhouse/cell-config.h> #define ARRAY_SIZE(a) sizeof(a) / sizeof(a[0]) struct { struct jailhouse_cell_desc cell; __u64 cpus[1]; struct jailhouse_memory mem_regions[4]; struct jailhouse_irqchip irqchips[1]; struct jailhouse_pci_device pci_devices[1]; } __attribute__((packed)) config = { .cell = { .signature = JAILHOUSE_CELL_DESC_SIGNATURE, .revision = JAILHOUSE_CONFIG_REVISION, .name = "nfer", .flags = JAILHOUSE_CELL_PASSIVE_COMMREG, .cpu_set_size = sizeof(config.cpus), .num_memory_regions = ARRAY_SIZE(config.mem_regions), .num_irqchips = ARRAY_SIZE(config.irqchips), .num_pci_devices = ARRAY_SIZE(config.pci_devices), .vpci_irq_base = 148-32, }, .cpus = { 0x2, }, .mem_regions = { /* UART */ { .phys_start = 0xff010000, .virt_start = 0xff010000, .size = 0x1000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED, }, /* RAM */ { .phys_start = 0x800a00000, .virt_start = 0, .size = 0x00010000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE, }, /* IVSHMEM shared memory region for 00:01.0 */ { .phys_start = 0x800700000, .virt_start = 0x800700000, .size = 0x100000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_ROOTSHARED, }, /* BRAM */ { .phys_start = 0x500000000, .virt_start = 0x500000000, .size = 0x100000, //1MB .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_ROOTSHARED, }, }, .irqchips = { /* GIC */ { .address = 0xf9010000, .pin_base = 32, .pin_bitmap = { 0, 0, 0, (1 << (148 - 128)) | (1 << (149 - 128)) | (1 << (150 - 128)) }, }, }, .pci_devices = { /* 00:01.0 */ { .type = JAILHOUSE_PCI_TYPE_IVSHMEM, .bdf = 1 << 3, .bar_mask = { 0xffff7000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, .shmem_region = 2, .shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED, .num_msix_vectors = 0, .domain = 0, }, }, };
