Basically, the MMU on both ARM architectures work in the same way. There are only slight differences in register naming and their content. But the 'same' set of registers needs to be written. By abstracting registers and their content to sysregs.h, we're now able to use the same MMU driver code for both architectures.
Device drivers will ID-map the regions they are touching: - Base address of the inmate, length 0x10000 (results in 2MiB) - Communication Region, length 0x1000 (results in 2MiB) - UART, if existent, length 0x1000 (results in 2MiB) - GIC[CD|DR], length 0x1000 (results in 2MiB) Signed-off-by: Ralf Ramsauer <[email protected]> --- inmates/lib/arm-common/gic-v2.c | 3 +++ inmates/lib/arm-common/gic-v3.c | 3 +++ inmates/lib/arm-common/printk.c | 6 ++++++ inmates/lib/arm-common/setup.c | 24 ++++++++++++++++++++++++ 4 files changed, 36 insertions(+) diff --git a/inmates/lib/arm-common/gic-v2.c b/inmates/lib/arm-common/gic-v2.c index e2c271c3..fbb55f68 100644 --- a/inmates/lib/arm-common/gic-v2.c +++ b/inmates/lib/arm-common/gic-v2.c @@ -63,6 +63,9 @@ static void gic_v2_enable(unsigned int irqn) static int gic_v2_init(void) { + map_range(GICC_V2_BASE, PAGE_SIZE, MAP_UNCACHED); + map_range(GICD_V2_BASE, PAGE_SIZE, MAP_UNCACHED); + mmio_write32(GICC_V2_BASE + GICC_CTLR, GICC_CTLR_GRPEN1); mmio_write32(GICC_V2_BASE + GICC_PMR, GICC_PMR_DEFAULT); mmio_write32(GICD_V2_BASE + GICD_CTLR, GICD_CTLR_ENABLE); diff --git a/inmates/lib/arm-common/gic-v3.c b/inmates/lib/arm-common/gic-v3.c index f98f5257..1118ec5f 100644 --- a/inmates/lib/arm-common/gic-v3.c +++ b/inmates/lib/arm-common/gic-v3.c @@ -60,6 +60,9 @@ static void gic_v3_enable(unsigned int irqn) static int gic_v3_init(void) { + map_range(GICD_V3_BASE, PAGE_SIZE, MAP_UNCACHED); + map_range(GICR_V3_BASE, PAGE_SIZE, MAP_UNCACHED); + arm_write_sysreg(ICC_CTLR_EL1, 0); arm_write_sysreg(ICC_PMR_EL1, 0xf0); arm_write_sysreg(ICC_IGRPEN1_EL1, ICC_IGRPEN1_EN); diff --git a/inmates/lib/arm-common/printk.c b/inmates/lib/arm-common/printk.c index c14d9da4..9dba55ff 100644 --- a/inmates/lib/arm-common/printk.c +++ b/inmates/lib/arm-common/printk.c @@ -112,6 +112,12 @@ static void console_init(void) chip->clock_reg = (void *)(unsigned long) cmdline_parse_int("con-clock-reg", CON_CLOCK_REG); + if (chip->base) + map_range(chip->base, PAGE_SIZE, MAP_UNCACHED); + + if (chip->clock_reg) + map_range(chip->clock_reg, PAGE_SIZE, MAP_UNCACHED); + chip->init(chip); if (chip->divider == 0) { diff --git a/inmates/lib/arm-common/setup.c b/inmates/lib/arm-common/setup.c index 073101b3..0eb81b76 100644 --- a/inmates/lib/arm-common/setup.c +++ b/inmates/lib/arm-common/setup.c @@ -82,4 +82,28 @@ void map_range(void *start, unsigned long size, enum map_type map_type) void arch_init_early(void) { + unsigned long mair, sctlr; + + map_range((void*)CONFIG_INMATE_BASE, 0x10000, MAP_CACHED); + map_range((void*)COMM_REGION_BASE, PAGE_SIZE, MAP_CACHED); + + /* + * ARMv7: Use attributes 0 and 1 in MAIR0 + * ARMv8: Use attributes 0 and 1 in MAIR + * + * Attributes 0: inner/outer: normal memory, outer write-back + * non-transient + * Attributes 1: device memory + */ + mair = MAIR_ATTR(1, MAIR_ATTR_DEVICE) | MAIR_ATTR(0, MAIR_ATTR_WBRWA); + arm_write_sysreg(MAIR, mair); + + arm_write_sysreg(TRANSL_CONT_REG, TRANSL_CONT_REG_SETTINGS); + + arm_write_sysreg(TTBR0, page_directory); + + arm_read_sysreg(SCTLR, sctlr); + sctlr |= SCTLR_MMU_CACHES; + arm_write_sysreg(SCTLR, SCTLR_MMU_CACHES); + /* MMU is enabled from now on */ } -- 2.17.0 -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
