Same for arm64, define system registers and settings that we will use later.
Signed-off-by: Ralf Ramsauer <[email protected]> --- inmates/lib/arm64/include/asm/sysregs.h | 30 +++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/inmates/lib/arm64/include/asm/sysregs.h b/inmates/lib/arm64/include/asm/sysregs.h index b2adde7d..41b07159 100644 --- a/inmates/lib/arm64/include/asm/sysregs.h +++ b/inmates/lib/arm64/include/asm/sysregs.h @@ -41,6 +41,36 @@ #ifndef __ASSEMBLY__ +#define SCTLR_EL1_I (1 << 12) +#define SCTLR_EL1_C (1 << 2) +#define SCTLR_EL1_M (1 << 0) + +#define SCTLR SCTLR_EL1 + +/* Enable MMU, data+instruction caches */ +#define SCTLR_MMU_CACHES (SCTLR_EL1_I | SCTLR_EL1_C | SCTLR_EL1_M) + +#define TCR_EL1_T0SZ_25 25 +#define TCR_EL1_IRGN0_WBWAC (0x1 << 8) +#define TCR_EL1_ORGN0_WBWAC (0x1 << 10) +#define TCR_EL1_SH0_IS (0x3 << 12) +#define TCR_EL1_TG0_4K (0x0 << 14) +#define TCR_EL1_IPC_256TB (0x5UL << 32) + +/* + * IPA size 48bit (256TiB), 4KiB granularity, and set inner/outer caches to + * write-back write-allocate cacheable and shareability attribute to inner + * shareable + */ +#define TRANSL_CONT_REG TCR_EL1 +#define TRANSL_CONT_REG_SETTINGS \ + TCR_EL1_IPC_256TB | TCR_EL1_TG0_4K | TCR_EL1_SH0_IS | \ + TCR_EL1_ORGN0_WBWAC | TCR_EL1_IRGN0_WBWAC | TCR_EL1_T0SZ_25 + +#define MAIR MAIR_EL1 + +#define TTBR0 TTBR0_EL1 + #define __stringify_1(x...) #x #define __stringify(x...) __stringify_1(x) -- 2.17.0 -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
