On 2018-09-04 13:29, Ralf Ramsauer wrote:
On 02/09/2018 17:49, Jan Kiszka wrote:
From: Jan Kiszka <[email protected]>

This can provide hints why latencies are not as low as expected, even
without any hypervisor exits.

Signed-off-by: Jan Kiszka <[email protected]>
---

Changes in v2:
  - hmpf, not all CPUs support this register...

like the Xeon E5 v4 (model 0x4f) in front of me...

According to Intel's SDM, there is no register MSR_SMI_COUNT for this
model (p. 248 f.), but register 0x34 isn't used for anything else.

Hmm, let's try to read it!

A first attempt returned 1825 across all cores, after a warm reboot it
increased to 182c, and after a cold reboot it increased again to 1835.
After the next reboot it dropped to 182f. Meh, doesn't look good. :-(

I don't know what the value reflects, probably nothing, but /maybe/ it's
a SMI count, though, I'll keep an eye on it.


A reboot (unless its kexec based) should reset that counter. It typically increases during early boot-up, e.g. while the BIOS is handling legacy devices accesses. However, your number is comparably high.

  - fix typo "MSR_MSI_COUNT"

  inmates/demos/x86/apic-demo.c | 45 ++++++++++++++++++++++++++++++++++++++++++-
  1 file changed, 44 insertions(+), 1 deletion(-)

diff --git a/inmates/demos/x86/apic-demo.c b/inmates/demos/x86/apic-demo.c
index ce03872e..65f6f55e 100644
--- a/inmates/demos/x86/apic-demo.c
+++ b/inmates/demos/x86/apic-demo.c
@@ -12,24 +12,61 @@
#include <inmate.h> +#define MSR_SMI_COUNT 0x34
+
  #define POLLUTE_CACHE_SIZE    (512 * 1024)
#define APIC_TIMER_VECTOR 32 static unsigned long expected_time;
  static unsigned long min = -1, max;
+static bool has_smi_count;
+static u32 initial_smis;
+
+unsigned int smi_count_models[] = {

can become static

Actually, static const.


+       0x37, 0x4a, 0x4d, 0x5a, 0x5d, 0x5c, 0x7a,
/* Silvermont */

Missing: 0x57, 0x85: Xeon Phi 3200/5200/7200 (ref. Intel SDM v4 p. 298)

I was copying from section 2.23 (MSR Index), but I missed the page break. And Intel missed 06_85 in that index. Hopefully not more.



+       0x1a, 0x1e, 0x1f, 0x2e,

/* Nehalem */

+       0x2a, 0x2d,

/* Sandy Bridge */


Can add the comments, thanks for checking.

Jan
--
Siemens AG, Corporate Technology, CT RDA IOT SES-DE
Corporate Competence Center Embedded Linux

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