[snip]
On 7/5/19 4:16 PM, Ralf Ramsauer wrote:
>>> I found the evil guy. It's inside apic_clear. The last call to the xapic:
>>>
>>> apic.c @ apic_clear
>>> /* Finally, reset the TPR again and disable the APIC */
>>> apic_ops.write(APIC_REG_TPR, 0);
>>> apic_ops.write(APIC_REG_SVR, 0xff);
>>>
>>> Disabling the xAPIC via APIC_REG_SVR will reset LVT0 and others to zero.
>> What?!?
> Yep.
>
> That's my instrumentation:
>
> diff --git a/hypervisor/arch/x86/apic.c b/hypervisor/arch/x86/apic.c
> index 7f51b062..d88ee237 100644
> --- a/hypervisor/arch/x86/apic.c
> +++ b/hypervisor/arch/x86/apic.c
> @@ -340,7 +340,12 @@ void apic_clear(void)
>
> /* Finally, reset the TPR again and disable the APIC */
> apic_ops.write(APIC_REG_TPR, 0);
> - apic_ops.write(APIC_REG_SVR, 0xff);
> +
> + printk("Before disabling: %x\n", apic_ops.read(APIC_REG_LVT0));
> + apic_ops.write(APIC_REG_SVR, 0xff);
> + printk("After disabling: %x\n", apic_ops.read(APIC_REG_LVT0));
> + apic_ops.write(APIC_REG_SVR, APIC_SVR_ENABLE_APIC | 0xff);
> + printk("After reenabling: %x\n", apic_ops.read(APIC_REG_LVT0));
> }
>
> static bool apic_valid_ipi_mode(u32 lo_val)
>
>
> And here is jailhouse output:
>
> Created cell "linux-x86-demo"
> Page pool usage after cell creation: mem 280/979, remap 16519/131072
> Cell "linux-x86-demo" can be loaded
> CPU 3 received SIPI, vector 100
> Started cell "linux-x86-demo"
> Before disabling: 10000
> After disabling: 0
> After reenabling: 0
> [...]
>
>
>> "The ASE bit when set to 0 disables the local APIC temporarily. When the
>> local APIC is disabled, SMI, NMI, INIT, Startup, Remote Read, and LINT
>> interrupts may be accepted; pending interrupts in the ISR and IRR are
>> held, but further fixed, lowest-priority, and ExtInt interrupts are not
>> accepted. All LVT entry mask bits are set and cannot be cleared."
>>
>> If that is not true for your hardware, it does not conform to its own spec.
> What can I say, it's not the first time that hardware doesn't conform to
> specs.
For the records: I checked this on an old AMD E350. I can't see the bug
there.
Ralf
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