Hi,
On 27/02/2020 15:24, [email protected] wrote:
> Hi all,
>
> I'd just like to add that I am experiencing the exact same issue as
> described by Ralf on an AMD EPYC 7351P.
aah, 'good' to hear!
> The stacktrace is the same as well:
>
> FATAL: Setting invalid LVT delivery mode (reg 35, value 00000700
>
> However, on my side I cannot get past this by just handing over the
> xAPIC enabled; I get the same trace..
> I added the printk's from Ralf's diff and get the same output:
> ...
> Before disabling: 10000
> After disabling: 0
> After reenabling: 0
Great. So we definitely have a systematic hardware bug that doesn't only
affect our CPU.
... Did I already post my local hacky workaround?
diff --git a/hypervisor/arch/x86/apic.c b/hypervisor/arch/x86/apic.c
index de691329..7f51b062 100644
--- a/hypervisor/arch/x86/apic.c
+++ b/hypervisor/arch/x86/apic.c
@@ -340,7 +340,7 @@ void apic_clear(void)
/* Finally, reset the TPR again and disable the APIC */
apic_ops.write(APIC_REG_TPR, 0);
- apic_ops.write(APIC_REG_SVR, 0xff);
+ //apic_ops.write(APIC_REG_SVR, 0xff);
}
static bool apic_valid_ipi_mode(u32 lo_val)
Maybe we could try to reach out to AMD via some kernel mailing list?
> ...
>
> I presume that by "hand over the xAPIC enabled" you mean disabling the
> write to APIC_REG_SVR? That's what I did but it did not do the trick
> unfortunately.
Yep. Andrej, did we have to adjust anything else?
It's been a while that we've been working on that issue, and I don't
have the exact details in mind.
However, Andrej wanted to pick up the topic again soon.
Thanks,
Ralf
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