On 09.01.20 16:55, Chase Conklin wrote:
The GICv3 architecture does not guarantee that writes to the list
registers are self-synchronizing. As a result, it is possible for a
valid interrupt to be written into a list register but have the empty
list register status register report that list register as not holding
a valid interrupt. Since the empty list register status registers are
used to indicate which list registers can be used to inject an
interrupt to a cell, it is possible for a valid list register entry to
be overwritten, dropping the corresponding interrupt.

Fixes: 2ce9d14ca4e2 ("arm: GICv3 initialisation")
Signed-off-by: Chase Conklin <[email protected]>
---
  hypervisor/arch/arm-common/gic-v3.c | 6 ++++++
  1 file changed, 6 insertions(+)

diff --git a/hypervisor/arch/arm-common/gic-v3.c 
b/hypervisor/arch/arm-common/gic-v3.c
index 906d9a8d..6a1d90f8 100644
--- a/hypervisor/arch/arm-common/gic-v3.c
+++ b/hypervisor/arch/arm-common/gic-v3.c
@@ -113,6 +113,12 @@ static void gicv3_write_lr(unsigned int reg, u64 val)
  __WRITE_LR8_15(7)
  #undef __WRITE_LR8_15
  }
+
+/*
+ * Ensure the write to the LR is visible to the GIC (so that ICH_ELRSR
+ * is updated to indicate that the just-written LR is no longer empty)
+ */
+isb();

Ah, good to know. May we have such issues elsewhere as well? GICv2 is
not affected because it uses MMIO accesses, right?

Unfortunately, both your patches got mangled by your mail client. Can
you resent, maybe directly via git send-email?

Thanks,
Jan

  }

  static int gicv3_init(void)
--
2.22.0

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