On 15.01.20 18:33, Chase Conklin wrote:
The GICv3 architecture does not guarantee that writes to the list registers are self-synchronizing. As a result, it is possible for a valid interrupt to be written into a list register but have the empty list register status register report that list register as not holding a valid interrupt. Since the empty list register status registers are used to indicate which list registers can be used to inject an interrupt to a cell, it is possible for a valid list register entry to be overwritten, dropping the corresponding interrupt.Fixes: 2ce9d14ca4e2 ("arm: GICv3 initialisation") Signed-off-by: Chase Conklin <[email protected]> --- hypervisor/arch/arm-common/gic-v3.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hypervisor/arch/arm-common/gic-v3.c b/hypervisor/arch/arm-common/gic-v3.c index 906d9a8d..6a1d90f8 100644 --- a/hypervisor/arch/arm-common/gic-v3.c +++ b/hypervisor/arch/arm-common/gic-v3.c @@ -113,6 +113,12 @@ static void gicv3_write_lr(unsigned int reg, u64 val) __WRITE_LR8_15(7) #undef __WRITE_LR8_15 } + + /* + * Ensure the write to the LR is visible to the GIC (so that ICH_ELRSR + * is updated to indicate that the just-written LR is no longer empty) + */ + isb(); }static int gicv3_init(void)
Thanks, applied to next. Jan -- Siemens AG, Corporate Technology, CT RDA IOT SES-DE Corporate Competence Center Embedded Linux -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/d/msgid/jailhouse-dev/3002c7cc-2ab9-6e06-0aec-28e43abf4ee4%40siemens.com.
