From: Nikhil Devshatwar <[email protected]> Typical SoCs tend to have hardware blocks where you have to partition the resources at a register level. e.g. pinmux, clock control, and other common registers need to be partitioned at register level granularity.
Adding jailhouse_mem_region for each register does not make sense because of the high number of such registers. A simple bitmap would be useful to describe the individual register ownership. Add support for jailhouse_regmap, where each bit indicates ownership of a register in the region specified. Update the HEADER_REVISION and struct parser formats to reflect new struct jailhouse_cell_desc Signed-off-by: Nikhil Devshatwar <[email protected]> --- include/jailhouse/cell-config.h | 22 ++++++++++++++++++++-- tools/jailhouse-cell-linux | 5 +++-- tools/jailhouse-hardware-check | 2 +- 3 files changed, 24 insertions(+), 5 deletions(-) diff --git a/include/jailhouse/cell-config.h b/include/jailhouse/cell-config.h index 30ec5d06..18d63dde 100644 --- a/include/jailhouse/cell-config.h +++ b/include/jailhouse/cell-config.h @@ -50,7 +50,7 @@ * Incremented on any layout or semantic change of system or cell config. * Also update HEADER_REVISION in tools. */ -#define JAILHOUSE_CONFIG_REVISION 12 +#define JAILHOUSE_CONFIG_REVISION 13 #define JAILHOUSE_CELL_NAME_MAXLEN 31 @@ -96,6 +96,7 @@ struct jailhouse_cell_desc { __u32 num_pci_devices; __u32 num_pci_caps; __u32 num_stream_ids; + __u32 num_regmaps; __u32 vpci_irq_base; @@ -241,6 +242,14 @@ struct jailhouse_pci_capability { #define JAILHOUSE_APIC_MODE_XAPIC 1 #define JAILHOUSE_APIC_MODE_X2APIC 2 +struct jailhouse_regmap { + __u64 reg_base; + __u32 reg_count; + __u8 reg_size; + __u32 flags; + __u32 reg_bitmap[8]; +} __attribute__((packed)); + #define JAILHOUSE_MAX_IOMMU_UNITS 8 #define JAILHOUSE_IOMMU_AMD 1 @@ -344,7 +353,8 @@ jailhouse_cell_config_size(struct jailhouse_cell_desc *cell) cell->num_pio_regions * sizeof(struct jailhouse_pio) + cell->num_pci_devices * sizeof(struct jailhouse_pci_device) + cell->num_pci_caps * sizeof(struct jailhouse_pci_capability) + - cell->num_stream_ids * sizeof(__u32); + cell->num_stream_ids * sizeof(__u32) + + cell->num_regmaps * sizeof(struct jailhouse_regmap); } static inline __u32 @@ -415,4 +425,12 @@ jailhouse_cell_stream_ids(const struct jailhouse_cell_desc *cell) cell->num_pci_caps * sizeof(struct jailhouse_pci_capability)); } +static inline const struct jailhouse_regmap * +jailhouse_cell_regmaps(const struct jailhouse_cell_desc *cell) +{ + return (const struct jailhouse_regmap *) + ((void *)jailhouse_cell_stream_ids(cell) + + cell->num_stream_ids * sizeof(__u32)); +} + #endif /* !_JAILHOUSE_CELL_CONFIG_H */ diff --git a/tools/jailhouse-cell-linux b/tools/jailhouse-cell-linux index 007a5c46..91bc4a6d 100755 --- a/tools/jailhouse-cell-linux +++ b/tools/jailhouse-cell-linux @@ -573,8 +573,8 @@ class PIORegion: class Config: - _HEADER_FORMAT = '=6sH32s4xIIIIIIIIIIQ8x32x' - _HEADER_REVISION = 12 + _HEADER_FORMAT = '=6sH32s4xIIIIIIIIIIIQ8x32x' + _HEADER_REVISION = 13 def __init__(self, config_file): self.data = config_file.read() @@ -591,6 +591,7 @@ class Config: self.num_pci_devices, self.num_pci_caps, self.num_stream_ids, + self.num_regmaps, self.vpci_irq_base, self.cpu_reset_address) = \ struct.unpack_from(Config._HEADER_FORMAT, self.data) diff --git a/tools/jailhouse-hardware-check b/tools/jailhouse-hardware-check index 375816e2..2db103c0 100755 --- a/tools/jailhouse-hardware-check +++ b/tools/jailhouse-hardware-check @@ -136,7 +136,7 @@ class Sysconfig: X86_MAX_IOMMU_UNITS = 8 X86_IOMMU_SIZE = 20 - HEADER_REVISION = 12 + HEADER_REVISION = 13 HEADER_FORMAT = '6sH' def __init__(self, path): -- 2.17.1 -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/d/msgid/jailhouse-dev/20200127135611.21302-3-nikhil.nd%40ti.com.
