On 27.01.20 17:13, Nikhil Devshatwar wrote:
On 27/01/20 9:30 pm, Ralf Ramsauer wrote:
On 27/01/2020 15:49, Jan Kiszka wrote:
On 27.01.20 14:56, nikhil.nd via Jailhouse wrote:
From: Nikhil Devshatwar<[email protected]>
This series adds support for partitioning registers across different
cells
in the Jailhouse. Jailhouse supports partitioning memory regions;
where it uses
MMU mapping for page aligned regions and subpage handler for non
aligned regions.
However, most of the embedded platforms will have common set of
registers which
need to be partitioned at the granularity of single register. One such
example is
the pinmux registers avaialble in many platforms including K3 J721e.
This series implements a regmap unit which allows to describe the
ownerhip of the
registers using a simple bitmap. This scales well when you have to
partition
hundreds of control module or pinmux registers.
Nikhil Devshatwar (4):
configs: arm64: k3-j721e-linux: Add USB mem_regions
core: Introduce regmaps in cell config for partitioning registers
core: Implement regmap unit for partitioning registers
configs: k3-j721e: Add regmaps for PADCONFIG registers
configs/arm64/k3-j721e-evm-linux-demo.c | 41 +++-
configs/arm64/k3-j721e-evm.c | 15 ++
hypervisor/Makefile | 2 +-
hypervisor/include/jailhouse/cell.h | 2 +
hypervisor/include/jailhouse/regmap.h | 47 +++++
hypervisor/regmap.c | 258 ++++++++++++++++++++++++
include/jailhouse/cell-config.h | 22 +-
tools/jailhouse-cell-linux | 5 +-
tools/jailhouse-hardware-check | 2 +-
9 files changed, 387 insertions(+), 7 deletions(-)
create mode 100644 hypervisor/include/jailhouse/regmap.h
create mode 100644 hypervisor/regmap.c
Worthwhile to discuss, indeed. The key question for me is how well it
could map on other SoCs. Ralf, do you think it could be that simple,
based on your experiments? Or could we also face scenarios where we
The question is what you try to achieve:
Jan, when you introduced subpaging, the goal was to allow to assign
devices to different domains, if multiple devices are located on the
same page. We can observe that pattern on many platforms, and subpaging
provides a "generic" solution.
So what do you try to achieve with subpaging on a byte-wise/bit-wise
granularity? Make a non-partitionable device partitionable? That will
only work for some rare cases.
The main intention here was not to partition peripheral devices, but
just the registers
which are not really related to any device.
Most SoCs will have something like this where pinmux registers,
efuse registers, internal muxes, MAC addresses, and other config options
are provided.
Can you point out another SoC that we support which would benefit from
this description method?
This series was intended to solve these kind of register partitioning.
So, subpaging does not scale when we have a scattered access map, right?
But can we use this description method to replace subpaging? The latter
registers an contiguous mmio dispatch region, your approach additionally
checks within that region a bitmap. A subpage entry can handle up to
PAGE_SIZE-1, a regmap currently only 256 bytes. I wonder if we can
combine both, maybe expand the memory region to optionally refer to a
bitmap for finer-grained access control.
Jan
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