I tried to make two different non-root cell by taking jetson-tx1-demo as an
example when I try to create cell it says resource busy. Then I make
another configuration as espresso-demo i was able to create cell but when I
tried to change communication region and UART region (I mean address) it
shows un-handled error but when I kept UART and communication address same
as the tx1-demo it was successfully loaded and started with tx1-demo.
Displaying result in the same serial port.
I have attached three configuration
1.jetson-tx1-demo(in built in jailhouse)
2.jetson-tx1-inmate1(configured by using 1 as template) (resource busy
error)
3.jetson-tx1-inmate2(configured by using espresso-demo as template)
4.jetson-tx1 root cell
Questions:
1. Do all cell have same UART, IVSHMEM, and communication
region(0x80000000; I checked with other arm64 cell also all of them have
same address why?)?
2. How can I direct output of each cell to different serial port?
3. Why there is resource busy error in second case?
4. I don't understand how to declare irqchip and pci_device for each cell
and root cell? (most difficult one)
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/*
* Jailhouse, a Linux-based partitioning hypervisor
*
* Configuration for Jailhouse Jetson TX1 board
*
* Copyright (C) 2016 Evidence Srl
*
* Authors:
* Claudio Scordino <[email protected]>
* Bruno Morelli <[email protected]>
* Luca Cuomo <[email protected]>
*
* This work is licensed under the terms of the GNU GPL, version 2. See
* the COPYING file in the top-level directory.
*
* NOTE: Add "mem=3968M vmalloc=512M" to the kernel command line.
*/
#include <jailhouse/types.h>
#include <jailhouse/cell-config.h>
#define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0]))
struct {
struct jailhouse_system header;
__u64 cpus[1];
struct jailhouse_memory mem_regions[44];
struct jailhouse_irqchip irqchips[2];
struct jailhouse_pci_device pci_devices[2];
} __attribute__((packed)) config = {
.header = {
.signature = JAILHOUSE_SYSTEM_SIGNATURE,
.revision = JAILHOUSE_CONFIG_REVISION,
.hypervisor_memory = {
.phys_start = 0x17c000000,
.size = 0x4000000,
},
.debug_console = {
.address = 0x70006000,
.size = 0x0040,
.flags = JAILHOUSE_CON1_TYPE_8250 |
JAILHOUSE_CON1_ACCESS_MMIO |
JAILHOUSE_CON1_REGDIST_4 |
JAILHOUSE_CON2_TYPE_ROOTPAGE,
},
.platform_info = {
.pci_mmconfig_base = 0x48000000,
.pci_mmconfig_end_bus = 0,
.pci_is_virtual = 1,
.pci_domain = -1,
.arm = {
.gic_version = 2,
.gicd_base = 0x50041000,
.gicc_base = 0x50042000,
.gich_base = 0x50044000,
.gicv_base = 0x50046000,
.maintenance_irq = 25,
}
},
.root_cell = {
.name = "Jetson-TX1",
.cpu_set_size = sizeof(config.cpus),
.num_memory_regions = ARRAY_SIZE(config.mem_regions),
.num_pci_devices = ARRAY_SIZE(config.pci_devices),
.num_irqchips = ARRAY_SIZE(config.irqchips),
/*On jetson TX1 IRQ from 212 to 223 are not assigned.
The root cell will use from 212 to 217.
Note: Jailhouse adds 32 (GIC's SPI)
to the .vpci_irq_base , so 180 is the base value*/
.vpci_irq_base = 180,
},
},
.cpus = {
0xf,
},
.mem_regions = {
/* APE 1 */ {
.phys_start = 0x00000000,
.virt_start = 0x00000000,
.size = 0x00D00000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* PCIE */ {
.phys_start = 0x01000000,
.virt_start = 0x01000000,
.size = 0x3F000000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* Data memory */ {
.phys_start = 0x040000000,
.virt_start = 0x040000000,
.size = 0x1000000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* host1x */ {
.phys_start = 0x50000000,
.virt_start = 0x50000000,
.size = 0x40000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* Graphics Host */ {
.phys_start = 0x54000000,
.virt_start = 0x54000000,
.size = 0x3000000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* GPU */ {
.phys_start = 0x57000000,
.virt_start = 0x57000000,
.size = 0x9000000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* Semaphores */ {
.phys_start = 0x60000000,
.virt_start = 0x60000000,
.size = 0x4000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* Legacy Interrupt Controller (ICTRL) */ {
.phys_start = 0x60004000,
.virt_start = 0x60004000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* TMR */ {
.phys_start = 0x60005000,
.virt_start = 0x60005000,
.size = 0x01000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* Clock and Reset */ {
.phys_start = 0x60006000,
.virt_start = 0x60006000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* Flow Controller */ {
.phys_start = 0x60007000,
.virt_start = 0x60007000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* AHB-DMA */ {
.phys_start = 0x60008000,
.virt_start = 0x60008000,
.size = 0x2000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* System registers, secure boot, activity monitor */ {
.phys_start = 0x6000c000,
.virt_start = 0x6000c000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* GPIOs + exception vectors */ {
.phys_start = 0x6000d000,
.virt_start = 0x6000d000,
.size = 0x2000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* IPATCH */ {
.phys_start = 0x60010000,
.virt_start = 0x60010000,
.size = 0x0010000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* APB-DMA + VGPIO */ {
.phys_start = 0x60020000,
.virt_start = 0x60020000,
.size = 0x5000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* MISC stuff (see datasheet) */ {
.phys_start = 0x70000000,
.virt_start = 0x70000000,
.size = 0x4000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* UARTs */ {
.phys_start = 0x70006000,
.virt_start = 0x70006000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* PWM Controller */ {
.phys_start = 0x7000a000,
.virt_start = 0x7000a000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* I2C + SPI*/ {
.phys_start = 0x7000c000,
.virt_start = 0x7000c000,
.size = 0x2000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* RTC + PMC + FUSE + KFUSE */ {
.phys_start = 0x7000e000,
.virt_start = 0x7000e000,
.size = 0x2000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* Sensors */ {
.phys_start = 0x70010000,
.virt_start = 0x70010000,
.size = 0x0008000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* MC */ {
.phys_start = 0x70019000,
.virt_start = 0x70019000,
.size = 0x7000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* SATA */ {
.phys_start = 0x70020000,
.virt_start = 0x70020000,
.size = 0x0010000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* HDA */ {
.phys_start = 0x70030000,
.virt_start = 0x70030000,
.size = 0x10000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* CLUSTER CLOCK */ {
.phys_start = 0x70040000,
.virt_start = 0x70040000,
.size = 0x0040000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* XUSB */ {
.phys_start = 0x70090000,
.virt_start = 0x70090000,
.size = 0x10000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* DDS */ {
.phys_start = 0x700a0000,
.virt_start = 0x700a0000,
.size = 0x0002000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* SDMMCs */ {
.phys_start = 0x700b0000,
.virt_start = 0x700b0000,
.size = 0x5000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* SPEEDO */ {
.phys_start = 0x700c0000,
.virt_start = 0x700c0000,
.size = 0x0008000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* DP2 + APB2JTAG */ {
.phys_start = 0x700e0000,
.virt_start = 0x700e0000,
.size = 0x0002000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* SOC_THERM */ {
.phys_start = 0x700e2000,
.virt_start = 0x700e2000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* MIPI_CAL */ {
.phys_start = 0x700e3000,
.virt_start = 0x700e3000,
.size = 0x100,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* SYSCTR0 */ {
.phys_start = 0x700f0000,
.virt_start = 0x700f0000,
.size = 0x0010000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* SYSCTR1 */ {
.phys_start = 0x70100000,
.virt_start = 0x70100000,
.size = 0x0010000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* DVFS */ {
.phys_start = 0x70110000,
.virt_start = 0x70110000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* APE 2 */ {
.phys_start = 0x702c0000,
.virt_start = 0x702c0000,
.size = 0x40000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* QSPI */ {
.phys_start = 0x70410000,
.virt_start = 0x70410000,
.size = 0x0001000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* STM + CSITE */ {
.phys_start = 0x71000000,
.virt_start = 0x71000000,
.size = 0x2000000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* AHB_A1 */ {
.phys_start = 0x78000000,
.virt_start = 0x78000000,
.size = 0x1000000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* AHB_A2 or USB */ {
.phys_start = 0x7c000000,
.virt_start = 0x7c000000,
.size = 0x2000000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* System RAM */ {
.phys_start = 0x80000000,
.virt_start = 0x80000000,
.size = 0xfc000000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE,
},
/* IVHSMEM 1*/ {
.phys_start = 0x17ba00000,
.virt_start = 0x17ba00000,
.size = 0x100000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE ,
},
/* IVHSMEM 2*/ {
.phys_start = 0x17bd00000,
.virt_start = 0x17bd00000,
.size = 0x100000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE ,
},
},
.irqchips = {
/* GIC */ {
.address = 0x50041000,
.pin_base = 32,
.pin_bitmap = {
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
},
},
/* GIC */ {
.address = 0x50041000,
.pin_base = 160,
.pin_bitmap = {
0xffffffff, 0xffffffff, 0xffffffff
},
},
},
.pci_devices = {
{
.type = JAILHOUSE_PCI_TYPE_IVSHMEM,
.bdf = 0x0 << 3,
.bar_mask = {
0xffffff00, 0xffffffff, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
/*num_msix_vectors needs to be 0 for INTx operation*/
.num_msix_vectors = 0,
.shmem_region = 42,
.shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED,
},
{
.type = JAILHOUSE_PCI_TYPE_IVSHMEM,
.bdf = 0xf << 3,
.bar_mask = {
0xffffff00, 0xffffffff, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
/*num_msix_vectors needs to be 0 for INTx operation*/
.num_msix_vectors = 0,
.shmem_region = 43,
.shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED,
},
},
};
/*
* Jailhouse, a Linux-based partitioning hypervisor
*
* Configuration for uart+ivshmem demo inmate on Nvidia Jetson TX1:
* 1 CPU, 64K RAM, serial port 0
*
* Copyright (c) 2018 Evidence Srl
*
* Authors:
* Luca Cuomo <[email protected]>
*
*
* This work is licensed under the terms of the GNU GPL, version 2. See
* the COPYING file in the top-level directory.
*/
#include <jailhouse/types.h>
#include <jailhouse/cell-config.h>
#define ARRAY_SIZE(a) sizeof(a) / sizeof(a[0])
struct {
struct jailhouse_cell_desc cell;
__u64 cpus[1];
struct jailhouse_memory mem_regions[4];
struct jailhouse_irqchip irqchips[2];
struct jailhouse_pci_device pci_devices[1];
} __attribute__((packed)) config = {
.cell = {
.signature = JAILHOUSE_CELL_DESC_SIGNATURE,
.revision = JAILHOUSE_CONFIG_REVISION,
.name = "jetson-tx1-demo",
.flags = JAILHOUSE_CELL_PASSIVE_COMMREG,
.cpu_set_size = sizeof(config.cpus),
.num_memory_regions = ARRAY_SIZE(config.mem_regions),
.num_irqchips = ARRAY_SIZE(config.irqchips),
.num_pci_devices = ARRAY_SIZE(config.pci_devices),
/*On Jetson TX1 the IRQs from 212 to 223 are not assigned.
The bare metal cell will use IRQs from 218 to 223.
Note: Jailhouse adds 32 (GIC's SPI) to the .vpci_irq_base,
so 186 is the base value*/
.vpci_irq_base = 186,
},
.cpus = {
0x8,
},
.mem_regions = {
/* UART */ {
.phys_start = 0x70006000,
.virt_start = 0x70006000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* RAM */ {
.phys_start = 0x17bfe0000,
.virt_start = 0,
.size = 0x00010000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,
},
/* communication region */ {
.virt_start = 0x80000000,
.size = 0x00001000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_COMM_REGION,
},
/* IVHSMEM 1*/ {
.phys_start = 0x17ba00000,
.virt_start = 0x17ba00000,
.size = 0x100000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_ROOTSHARED,
},
/* IVHSMEM 2*/ /*{
.phys_start = 0x17bd00000,
.virt_start = 0x17bd00000,
.size = 0x100000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_ROOTSHARED ,
},*/ //IVHSMEM 2 used in jetson-tx1-inmate1
},
.irqchips = {
/* GIC */ {
.address = 0x50041000,
.pin_base = 32,
/* Interrupts:
46 for UART C */
.pin_bitmap = {
0,
1<<(46-32)
},
},
/* GIC */ {
.address = 0x50041000,
.pin_base = 160,
/* Interrupts:
186 for IVSHMEM,
belongs to the bare metal cell */
.pin_bitmap = {
0,
3<<(186-160)
},
},
},
.pci_devices = {
{
.type = JAILHOUSE_PCI_TYPE_IVSHMEM,
.bdf = 0x0 << 3,
.bar_mask = {
0xffffff00, 0xffffffff, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
/* num_msix_vectors needs to be 0 for INTx operation*/
.num_msix_vectors = 0,
.shmem_region = 3, /* must be no of IVSHMEM region above */
.shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED,
},
/*{
.type = JAILHOUSE_PCI_TYPE_IVSHMEM,
.bdf = 0xf << 3,
.bar_mask = {
0xffffff00, 0xffffffff, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
/* num_msix_vectors needs to be 0 for INTx operation*/
/* .num_msix_vectors = 0,
.shmem_region = 4, /* must be no of IVSHMEM region above */
/* .shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED,
},*/
},
};
/*this cell is created and loaded successfully while the error obtained while changining UART adderss alone and Communication
region alone is placed in comments*/
#include <jailhouse/types.h>
#include <jailhouse/cell-config.h>
#define ARRAY_SIZE(a) sizeof(a) / sizeof(a[0])
struct {
struct jailhouse_cell_desc cell;
__u64 cpus[1];
struct jailhouse_memory mem_regions[3];
//struct jailhouse_irqchip irqchips[2];
//struct jailhouse_pci_device pci_devices[2];
} __attribute__((packed)) config = {
.cell = {
.signature = JAILHOUSE_CELL_DESC_SIGNATURE,
.revision = JAILHOUSE_CONFIG_REVISION,
.name = "jetson-tx1-inmate2",
.flags = JAILHOUSE_CELL_PASSIVE_COMMREG,
.cpu_set_size = sizeof(config.cpus),
.num_memory_regions = ARRAY_SIZE(config.mem_regions),
.num_irqchips = 0, //ARRAY_SIZE(config.irqchips),
.num_pci_devices = 0, //ARRAY_SIZE(config.pci_devices),
//.vpci_irq_base = 186,
},
.cpus = {
0x4,
},
.mem_regions = {
/* UART */ {
.phys_start = 0x70006000,/*when change to 0x70006200 (address of UARTC )
unhandlled error at 0x70006024 when loading cell*/
.virt_start = 0x70006000,
.size = 0x1000,//size decress to oxe00 for 0x70006200
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED,
},
/* RAM */ {
.phys_start = 0x17a000000,
.virt_start = 0,
.size = 0x00010000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA |
JAILHOUSE_MEM_LOADABLE,
},
/* communication region */ {
.virt_start = 0x80000000,//when change to 0x80001000 unhandlled error at 0x80000006 when loading cell
.size = 0x00001000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_COMM_REGION,
},
}
};
#include <jailhouse/types.h>
#include <jailhouse/cell-config.h>
#define ARRAY_SIZE(a) sizeof(a) / sizeof(a[0])
struct {
struct jailhouse_cell_desc cell;
__u64 cpus[1];
struct jailhouse_memory mem_regions[4];
struct jailhouse_irqchip irqchips[2];
struct jailhouse_pci_device pci_devices[1];
} __attribute__((packed)) config = {
.cell = {
.signature = JAILHOUSE_CELL_DESC_SIGNATURE,
.revision = JAILHOUSE_CONFIG_REVISION,
.name = "jetson-tx1-inmate1",
.flags = JAILHOUSE_CELL_PASSIVE_COMMREG,
.cpu_set_size = sizeof(config.cpus),
.num_memory_regions = ARRAY_SIZE(config.mem_regions),
.num_irqchips = ARRAY_SIZE(config.irqchips),
.num_pci_devices = ARRAY_SIZE(config.pci_devices),
.vpci_irq_base = 190,//186 in tx1-demo
},
.cpus = {
0x4,
},
.mem_regions = {
/* UART */ {
.phys_start = 0x70006000,
.virt_start = 0x70006000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},//same as tx1-demo
/* RAM */ {
.phys_start = 0x17a000000,//0xbfe000000 in tx1-demo
.virt_start = 0,
.size = 0x00010000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,
},
/* communication region */ {
.virt_start = 0x80000000,
.size = 0x00001000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_COMM_REGION,
},//same as tx1-demo
/*IVHSMEM 2*/ {
.phys_start = 0x17bd00000,
.virt_start = 0x17bd00000,
.size = 0x100000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_ROOTSHARED ,
},
},
.irqchips = {
/* GIC */ {
.address = 0x50041000,
.pin_base = 32,
/* Interrupts:
37 for UART B */
.pin_bitmap = {
0,
1<<(37-32)//46-32 for tx1-demo
},
},
/* GIC */ {
.address = 0x50041000,
.pin_base = 160,
/* Interrupts:
190 for IVSHMEM,
belongs to the bare metal cell */
.pin_bitmap = {
0,
3<<(190-160) //186-160 for tx1-demo
},
},
},
.pci_devices = {
{
.type = JAILHOUSE_PCI_TYPE_IVSHMEM,
.bdf = 0x0 << 3,
.bar_mask = {
0x00000000, 0x00000000, 0xffffffff,
0xffffffff, 0x00000000, 0x00000000,
},
/* num_msix_vectors needs to be 0 for INTx operation*/
.num_msix_vectors = 0,
.shmem_region = 3, /* must be no of IVSHMEM region above */
.shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED,
},
},
};
