I get confused how to configure for different serial output for two
inmates, can you help me on this. I have two cell and they are displaying
result on same serial output currently.
Root cell is same as before jetson-tx1.c
First cell configuration:
#include <jailhouse/cell-config.h>
#define ARRAY_SIZE(a) sizeof(a) / sizeof(a[0])
struct {
struct jailhouse_cell_desc cell;
__u64 cpus[1];
struct jailhouse_memory mem_regions[5];
struct jailhouse_irqchip irqchips[2];
struct jailhouse_pci_device pci_devices[2];
} __attribute__((packed)) config = {
.cell = {
.signature = JAILHOUSE_CELL_DESC_SIGNATURE,
.revision = JAILHOUSE_CONFIG_REVISION,
.name = "jetson-tx1-demo",
.flags = JAILHOUSE_CELL_PASSIVE_COMMREG,
.cpu_set_size = sizeof(config.cpus),
.num_memory_regions = ARRAY_SIZE(config.mem_regions),
.num_irqchips = ARRAY_SIZE(config.irqchips),
.num_pci_devices = ARRAY_SIZE(config.pci_devices),
/*On Jetson TX1 the IRQs from 212 to 223 are not assigned.
The bare metal cell will use IRQs from 218 to 223.
Note: Jailhouse adds 32 (GIC's SPI) to the .vpci_irq_base,
so 186 is the base value*/
.vpci_irq_base = 186,
},
.cpus = {
0x8,
},
.mem_regions = {
/* UART */ {
.phys_start = 0x70006000,
.virt_start = 0x70006000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* RAM */ {
.phys_start = 0x17bfe0000,
.virt_start = 0,
.size = 0x00010000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,
},
/* communication region */ {
.virt_start = 0x80000000,
.size = 0x00001000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_COMM_REGION,
},
/* IVHSMEM 1*/ {
.phys_start = 0x17ba00000,
.virt_start = 0x17ba00000,
.size = 0x100000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_ROOTSHARED,
},
/* IVHSMEM 2*/ {
.phys_start = 0x17bd00000,
.virt_start = 0x17bd00000,
.size = 0x100000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_ROOTSHARED ,
},
},
.irqchips = {
/* GIC */ {
.address = 0x50041000,
.pin_base = 32,
/* Interrupts:
46 for UART C */
.pin_bitmap = {
0,
1<<(46-32)
},
},
/* GIC */ {
.address = 0x50041000,
.pin_base = 160,
/* Interrupts:
186 for IVSHMEM,
belongs to the bare metal cell */
.pin_bitmap = {
0,
3<<(186-160)
},
},
},
.pci_devices = {
{
.type = JAILHOUSE_PCI_TYPE_IVSHMEM,
.bdf = 0x0 << 3,
.bar_mask = {
0xffffff00, 0xffffffff, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
/* num_msix_vectors needs to be 0 for INTx operation*/
.num_msix_vectors = 0,
.shmem_region = 3, /* must be no of IVSHMEM region above */
.shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED,
},
{
.type = JAILHOUSE_PCI_TYPE_IVSHMEM,
.bdf = 0xf << 3,
.bar_mask = {
0xffffff00, 0xffffffff, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
SECOND cell configuration:
#include <jailhouse/types.h>
#include <jailhouse/cell-config.h>
#define ARRAY_SIZE(a) sizeof(a) / sizeof(a[0])
struct {
struct jailhouse_cell_desc cell;
__u64 cpus[1];
struct jailhouse_memory mem_regions[3];
//struct jailhouse_irqchip irqchips[2];
//struct jailhouse_pci_device pci_devices[2];
} __attribute__((packed)) config = {
.cell = {
.signature = JAILHOUSE_CELL_DESC_SIGNATURE,
.revision = JAILHOUSE_CONFIG_REVISION,
.name = "jetson-tx1-demo1",
.flags = JAILHOUSE_CELL_PASSIVE_COMMREG,
.cpu_set_size = sizeof(config.cpus),
.num_memory_regions = ARRAY_SIZE(config.mem_regions),
.num_irqchips = 0, //ARRAY_SIZE(config.irqchips),
.num_pci_devices = 0, //ARRAY_SIZE(config.pci_devices),
//.vpci_irq_base = 186,
},
.cpus = {
0x4,
},
.mem_regions = {
/* UART */ {
.phys_start = 0x70006000,
.virt_start = 0x70006000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED,
},
/* RAM */ {
.phys_start = 0x17a000000,
.virt_start = 0,
.size = 0x00010000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA |
JAILHOUSE_MEM_LOADABLE,
},
/* communication region */ {
.virt_start = 0x80000000,
.size = 0x00001000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_COMM_REGION,
},
}
};
/* num_msix_vectors needs to be 0 for INTx operation*/
.num_msix_vectors = 0,
.shmem_region = 4, /* must be no of IVSHMEM region above */
.shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED,
},
},
};
#include <jailhouse/types.h>
On Friday, March 13, 2020 at 1:15:32 PM UTC-5, Jan Kiszka wrote:
>
> On 13.03.20 18:40, Saroj Sapkota wrote:
> > I tried to make two different non-root cell by taking jetson-tx1-demo as
> > an example when I try to create cell it says resource busy. Then I make
> > another configuration as espresso-demo i was able to create cell but
> > when I tried to change communication region and UART region (I mean
> > address) it shows un-handled error but when I kept UART and
> > communication address same as the tx1-demo it was successfully loaded
> > and started with tx1-demo. Displaying result in the same serial port.
> > I have attached three configuration
> > 1.jetson-tx1-demo(in built in jailhouse)
> > 2.jetson-tx1-inmate1(configured by using 1 as template) (resource busy
> > error)
> > 3.jetson-tx1-inmate2(configured by using espresso-demo as template)
> > 4.jetson-tx1 root cell
>
> There are several example cases in the tree that contain non-root
> configs which can be active at the same time, e.g.,
> qemu-arm64-linux-demo and qemu-arm64-inmate-demo or also the
> zynqmp-zcu102-linux-demo and
> zynqmp-zcu102-linux-demo-2.
>
> > Questions:
> > 1. Do all cell have same UART, IVSHMEM, and communication
> > region(0x80000000; I checked with other arm64 cell also all of them have
> > same address why?)?
>
> Comm region is a virtual resource. It can be mapped anywhere where there
> is space - and where the guests expects it. So we ended up at
> 0x800000000 on arm64.
>
> UART is a physical resource. When it's mapped multiple times it means
> both guests may access it - which easily ends up in an output mess at
> best. So, it is typically given one non-root cell while the root still
> has access but does not make use of it.
>
> The shared memory is the same for all connected guests of the same link,
> at least its physical address. That makes it, well, shared.
>
> > 2. How can I direct output of each cell to different serial port?
>
> By assigning different ports and configuring different console entries
> in the cell config (for bare-metal inmates) or adjusting the inmate
> device tree (for Linux inmates).
>
> > 3. Why there is resource busy error in second case?
>
> Both cells are supposed to use the same CPU - that is not working with
> Jailhouse. We only hand out exclusively used CPUs.
>
> > 4. I don't understand how to declare irqchip and pci_device for each
> > cell and root cell? (most difficult one)
>
> PCI assignment (except for virtual ivshmem devices) is not supported on
> your target (missing IOMMU, missing generic PCI host controller). All
> you can do is give one inmate exclusive access to a physical host
> controller, thus all devices behind it. Shouldn't be many on the TX1,
> though. For the pattern of configuring ivshmem devices, study e.g.
> qemu-arm64 configs. Except for the ivshmem memory addresses, you may
> copy those.
>
> The irqchip config of inmates is first of all copy from the root cell,
> just with the pin_bitmap reduces to those external interrupts that the
> inmate shall exclusively(!) use. Interrupts are associated with physical
> devices (check what Linux in the root cell reports when it still has
> access) or with the virtual ivshmem devices (vpci_irq_base + ivshmem PCI
> slot number (PCI device number, that's the Device in
> Bus:Device.Function, modulo 4).
>
> Hope that helps a bit.
>
> Jan
>
> --
> Siemens AG, Corporate Technology, CT RDA IOT SES-DE
> Corporate Competence Center Embedded Linux
>
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