On 21.08.20 04:49, [email protected] wrote: > From: Peng Fan <[email protected]> > > Set bit 30 of FPEXC32_EL2 to enables access to the Advanced SIMD and > floating-point functionality from all Exception levels. > > Set CPACR_EL1.FPEN to not trap accessing to SIMD or floating point > registers. > > Reported-by: Alice Guo <[email protected]> > Signed-off-by: Peng Fan <[email protected]> > --- > > V2: > Add Macros > Use u64 for fpexc32_el2. > > hypervisor/arch/arm64/control.c | 7 ++++++- > hypervisor/arch/arm64/include/asm/sysregs.h | 4 ++++ > 2 files changed, 10 insertions(+), 1 deletion(-) > > diff --git a/hypervisor/arch/arm64/control.c b/hypervisor/arch/arm64/control.c > index 7bc3cab1..cd90b5fc 100644 > --- a/hypervisor/arch/arm64/control.c > +++ b/hypervisor/arch/arm64/control.c > @@ -21,6 +21,7 @@ > void arm_cpu_reset(unsigned long pc, bool aarch32) > { > u64 hcr_el2; > + u64 fpexc32_el2; > > /* put the cpu in a reset state */ > /* AARCH64_TODO: handle big endian support */ > @@ -43,7 +44,7 @@ void arm_cpu_reset(unsigned long pc, bool aarch32) > arm_write_sysreg(AFSR1_EL1, 0); > arm_write_sysreg(AMAIR_EL1, 0); > arm_write_sysreg(CONTEXTIDR_EL1, 0); > - arm_write_sysreg(CPACR_EL1, 0); > + arm_write_sysreg(CPACR_EL1, CPACR_EL1_FPEN(3)); > arm_write_sysreg(CSSELR_EL1, 0); > arm_write_sysreg(ESR_EL1, 0); > arm_write_sysreg(FAR_EL1, 0); > @@ -57,6 +58,10 @@ void arm_cpu_reset(unsigned long pc, bool aarch32) > arm_write_sysreg(TTBR1_EL1, 0); > arm_write_sysreg(VBAR_EL1, 0); > > + arm_read_sysreg(FPEXC32_EL2, fpexc32_el2); > + fpexc32_el2 |= FPEXC_EL2_EN_BIT; > + arm_write_sysreg(FPEXC32_EL2, fpexc32_el2); > + > /* wipe timer registers */ > arm_write_sysreg(CNTP_CTL_EL0, 0); > arm_write_sysreg(CNTP_CVAL_EL0, 0); > diff --git a/hypervisor/arch/arm64/include/asm/sysregs.h > b/hypervisor/arch/arm64/include/asm/sysregs.h > index 56f0ce0a..378fecd8 100644 > --- a/hypervisor/arch/arm64/include/asm/sysregs.h > +++ b/hypervisor/arch/arm64/include/asm/sysregs.h > @@ -163,6 +163,10 @@ > /* exception level in SPSR_ELx */ > #define SPSR_EL(spsr) (((spsr) & 0xc) >> 2) > > +#define CPACR_EL1_FPEN(x) ((x) << 20)
I've replaced that with #define CPACR_EL1_FPEN_ALL (3UL << 20) > + > +#define FPEXC_EL2_EN_BIT (1UL << 30) > + > #ifndef __ASSEMBLY__ > > #include <jailhouse/string.h> > All 5 applied to next. Thanks, Jan -- Siemens AG, Corporate Technology, CT RDA IOT SES-DE Corporate Competence Center Embedded Linux -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/d/msgid/jailhouse-dev/bf6de4b9-053a-b7fb-5cb5-8bead3939315%40siemens.com.
