Branch: refs/heads/next
Home: https://github.com/siemens/jailhouse
Commit: e69184339a05ddfcf4949db12f5606e7cce1730c
https://github.com/siemens/jailhouse/commit/e69184339a05ddfcf4949db12f5606e7cce1730c
Author: Jan Kiszka <[email protected]>
Date: 2020-12-25 (Fri, 25 Dec 2020)
Changed paths:
M hypervisor/arch/arm/Makefile
Log Message:
-----------
arm: Enforce soft-float ABI
Required with newer gcc as we may otherwise "gain" vector instructions
that are not supported by Jailhouse. This is analogously to the kernel.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 1ea32307282e71282bb5cbf65af754abdbe3fbfa
https://github.com/siemens/jailhouse/commit/1ea32307282e71282bb5cbf65af754abdbe3fbfa
Author: Jan Kiszka <[email protected]>
Date: 2020-12-26 (Sat, 26 Dec 2020)
Changed paths:
M hypervisor/arch/arm/entry.S
Log Message:
-----------
arm: entry: Drop broken attempt to restore CPSR
This is neither the proper way to restor CPSR (we do not return to Linux
on error via eret) nor is this needed (no relevant change to CPSR done
if we return prior to switching to EL2). So drop this.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: d9f658ba17fcef567a0b80d1a610a325c18c0e13
https://github.com/siemens/jailhouse/commit/d9f658ba17fcef567a0b80d1a610a325c18c0e13
Author: Jan Kiszka <[email protected]>
Date: 2020-12-26 (Sat, 26 Dec 2020)
Changed paths:
M hypervisor/arch/arm/control.c
M hypervisor/arch/arm/mmio.c
M hypervisor/arch/arm/setup.c
M hypervisor/arch/arm/traps.c
Log Message:
-----------
arm: Fix access to SPSR from EL2
When in EL2, banked SPSR_hyp is not accessible. We rather want SPSR of
the current mode. For writing, that means appending fsxc which selects
all bits. Reading means dropping the bank suffix.
Noticed via QEMU. Real HW might have done the intended access so far.
Signed-off-by: Jan Kiszka <[email protected]>
Compare:
https://github.com/siemens/jailhouse/compare/3ad66a08f2e1...d9f658ba17fc
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