On 08.02.21 12:24, Kizska Jan wrote:
>Something may have caused a subpage MMIO region to be created (page-unaligned
>memory region). If that region split-up didn't exist in the root cell already,
>things will fail. But I suspect that subpage is rather a symptom, not the
>>cause.
>Where there any compiler warnings when building the config? I would also
>recommend checking our configs via "jailhouse config check root.cell
>cell1.cell cell2.cell ...". Or share what you created.
>Jan
>--
>Siemens AG, T RDA IOT
>Corporate Competence Center Embedded Linux
There are no warning during compilation and jailhouse config check command says
it is everything correct.
#jailhouse config check sysconfig.cell core1-cell.cell core2-cell.cell
core3-cell.cell core4-cell.cell core5-cell.cell
Reading configuration set:
Root cell: RootCell (sysconfig.cell)
Non-root cell: core1-cell (core1-cell.cell)
Non-root cell: core2-cell (core2-cell.cell)
Non-root cell: core3-cell (core3-cell.cell)
Non-root cell: core4-cell (core4-cell.cell)
Non-root cell: core5-cell (core5-cell.cell)
Overlapping memory regions inside cell: None
Overlapping memory regions with hypervisor: None
Missing PCI MMCONFIG interceptions: None
Missing IOMMU interceptions: None
Missing resource interceptions for architecture x86: None
Attached to the mail the cell files I'm using. The .bin file is the same as for
apic-demo.
Thanks a lot for the help :)
Markel.
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#include <jailhouse/types.h>
#include <jailhouse/cell-config.h>
struct {
struct jailhouse_cell_desc cell;
__u64 cpus[1];
struct jailhouse_memory mem_regions[2];
struct jailhouse_cache cache_regions[1];
struct jailhouse_pio pio_regions[3];
} __attribute__((packed)) config = {
.cell = {
.signature = JAILHOUSE_CELL_DESC_SIGNATURE,
.revision = JAILHOUSE_CONFIG_REVISION,
.name = "core0-cell",
.flags = JAILHOUSE_CELL_VIRTUAL_CONSOLE_PERMITTED,
.cpu_set_size = sizeof(config.cpus),
.num_memory_regions = ARRAY_SIZE(config.mem_regions),
.num_cache_regions = ARRAY_SIZE(config.cache_regions),
.num_irqchips = 0,
.num_pio_regions = ARRAY_SIZE(config.pio_regions),
.num_pci_devices = 0,
.console = {
.type = JAILHOUSE_CON_TYPE_8250,
.flags = JAILHOUSE_CON_ACCESS_PIO,
.address = 0x3f8,
},
},
.cpus = {
0x01,
},
.mem_regions = {
/* RAM */ {
.phys_start = 0x3f2f4240,
.virt_start = 0,
.size = 0x4c4b400,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,
},
/* communication region */ {
.virt_start = 0x4c4b400,
.size = 0x00001000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_COMM_REGION,
},
},
.cache_regions = {
{
.start = 0,
.size = 2,
.type = JAILHOUSE_CACHE_L3,
},
},
.pio_regions = {
PIO_RANGE(0x2f8, 8), /* serial 2 */
PIO_RANGE(0x3f8, 8), /* serial 1 */
PIO_RANGE(0xe010, 8), /* OXPCIe952 serial */
},
};
#include <jailhouse/types.h>
#include <jailhouse/cell-config.h>
struct {
struct jailhouse_cell_desc cell;
__u64 cpus[1];
struct jailhouse_memory mem_regions[2];
struct jailhouse_cache cache_regions[1];
struct jailhouse_pio pio_regions[3];
} __attribute__((packed)) config = {
.cell = {
.signature = JAILHOUSE_CELL_DESC_SIGNATURE,
.revision = JAILHOUSE_CONFIG_REVISION,
.name = "core1-cell",
.flags = JAILHOUSE_CELL_VIRTUAL_CONSOLE_PERMITTED,
.cpu_set_size = sizeof(config.cpus),
.num_memory_regions = ARRAY_SIZE(config.mem_regions),
.num_cache_regions = ARRAY_SIZE(config.cache_regions),
.num_irqchips = 0,
.num_pio_regions = ARRAY_SIZE(config.pio_regions),
.num_pci_devices = 0,
.console = {
.type = JAILHOUSE_CON_TYPE_8250,
.flags = JAILHOUSE_CON_ACCESS_PIO,
.address = 0x3f8,
},
},
.cpus = {
0x2,
},
.mem_regions = {
/* RAM */ {
.phys_start = 0x44033880,
.virt_start = 0,
.size = 0x4c4b400,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,
},
/* communication region */ {
.virt_start = 0x4c4b400,
.size = 0x00001000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_COMM_REGION,
},
},
.cache_regions = {
{
.start = 0,
.size = 2,
.type = JAILHOUSE_CACHE_L3,
},
},
.pio_regions = {
PIO_RANGE(0x2f8, 8), /* serial 2 */
PIO_RANGE(0x3f8, 8), /* serial 1 */
PIO_RANGE(0xe010, 8), /* OXPCIe952 serial */
},
};
#include <jailhouse/types.h>
#include <jailhouse/cell-config.h>
struct {
struct jailhouse_cell_desc cell;
__u64 cpus[1];
struct jailhouse_memory mem_regions[2];
struct jailhouse_cache cache_regions[1];
struct jailhouse_pio pio_regions[3];
} __attribute__((packed)) config = {
.cell = {
.signature = JAILHOUSE_CELL_DESC_SIGNATURE,
.revision = JAILHOUSE_CONFIG_REVISION,
.name = "core2-cell",
.flags = JAILHOUSE_CELL_VIRTUAL_CONSOLE_PERMITTED,
.cpu_set_size = sizeof(config.cpus),
.num_memory_regions = ARRAY_SIZE(config.mem_regions),
.num_cache_regions = ARRAY_SIZE(config.cache_regions),
.num_irqchips = 0,
.num_pio_regions = ARRAY_SIZE(config.pio_regions),
.num_pci_devices = 0,
.console = {
.type = JAILHOUSE_CON_TYPE_8250,
.flags = JAILHOUSE_CON_ACCESS_PIO,
.address = 0x3f8,
},
},
.cpus = {
0x04,
},
.mem_regions = {
/* RAM */ {
.phys_start = 0x48d72ec0,
.virt_start = 0,
.size = 0x4c4b400,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,
},
/* communication region */ {
.virt_start = 0x4c4b400,
.size = 0x00001000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_COMM_REGION,
},
},
.cache_regions = {
{
.start = 0,
.size = 2,
.type = JAILHOUSE_CACHE_L3,
},
},
.pio_regions = {
PIO_RANGE(0x2f8, 8), /* serial 2 */
PIO_RANGE(0x3f8, 8), /* serial 1 */
PIO_RANGE(0xe010, 8), /* OXPCIe952 serial */
},
};
#include <jailhouse/types.h>
#include <jailhouse/cell-config.h>
struct {
struct jailhouse_cell_desc cell;
__u64 cpus[1];
struct jailhouse_memory mem_regions[2];
struct jailhouse_cache cache_regions[1];
struct jailhouse_pio pio_regions[3];
} __attribute__((packed)) config = {
.cell = {
.signature = JAILHOUSE_CELL_DESC_SIGNATURE,
.revision = JAILHOUSE_CONFIG_REVISION,
.name = "core3-cell",
.flags = JAILHOUSE_CELL_VIRTUAL_CONSOLE_PERMITTED,
.cpu_set_size = sizeof(config.cpus),
.num_memory_regions = ARRAY_SIZE(config.mem_regions),
.num_cache_regions = ARRAY_SIZE(config.cache_regions),
.num_irqchips = 0,
.num_pio_regions = ARRAY_SIZE(config.pio_regions),
.num_pci_devices = 0,
.console = {
.type = JAILHOUSE_CON_TYPE_8250,
.flags = JAILHOUSE_CON_ACCESS_PIO,
.address = 0x3f8,
},
},
.cpus = {
0x08,
},
.mem_regions = {
/* RAM */ {
.phys_start = 0x4dab2500,
.virt_start = 0,
.size = 0x4c4b400,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,
},
/* communication region */ {
.virt_start = 0x4c4b400,
.size = 0x00001000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_COMM_REGION,
},
},
.cache_regions = {
{
.start = 0,
.size = 2,
.type = JAILHOUSE_CACHE_L3,
},
},
.pio_regions = {
PIO_RANGE(0x2f8, 8), /* serial 2 */
PIO_RANGE(0x3f8, 8), /* serial 1 */
PIO_RANGE(0xe010, 8), /* OXPCIe952 serial */
},
};
#include <jailhouse/types.h>
#include <jailhouse/cell-config.h>
struct {
struct jailhouse_cell_desc cell;
__u64 cpus[1];
struct jailhouse_memory mem_regions[2];
struct jailhouse_cache cache_regions[1];
struct jailhouse_pio pio_regions[3];
} __attribute__((packed)) config = {
.cell = {
.signature = JAILHOUSE_CELL_DESC_SIGNATURE,
.revision = JAILHOUSE_CONFIG_REVISION,
.name = "core4-cell",
.flags = JAILHOUSE_CELL_VIRTUAL_CONSOLE_PERMITTED,
.cpu_set_size = sizeof(config.cpus),
.num_memory_regions = ARRAY_SIZE(config.mem_regions),
.num_cache_regions = ARRAY_SIZE(config.cache_regions),
.num_irqchips = 0,
.num_pio_regions = ARRAY_SIZE(config.pio_regions),
.num_pci_devices = 0,
.console = {
.type = JAILHOUSE_CON_TYPE_8250,
.flags = JAILHOUSE_CON_ACCESS_PIO,
.address = 0x3f8,
},
},
.cpus = {
0x10,
},
.mem_regions = {
/* RAM */ {
.phys_start = 0x527f1b40,
.virt_start = 0,
.size = 0x4c4b400,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,
},
/* communication region */ {
.virt_start = 0x4c4b400,
.size = 0x00001000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_COMM_REGION,
},
},
.cache_regions = {
{
.start = 0,
.size = 2,
.type = JAILHOUSE_CACHE_L3,
},
},
.pio_regions = {
PIO_RANGE(0x2f8, 8), /* serial 2 */
PIO_RANGE(0x3f8, 8), /* serial 1 */
PIO_RANGE(0xe010, 8), /* OXPCIe952 serial */
},
};
#include <jailhouse/types.h>
#include <jailhouse/cell-config.h>
struct {
struct jailhouse_cell_desc cell;
__u64 cpus[1];
struct jailhouse_memory mem_regions[2];
struct jailhouse_cache cache_regions[1];
struct jailhouse_pio pio_regions[3];
} __attribute__((packed)) config = {
.cell = {
.signature = JAILHOUSE_CELL_DESC_SIGNATURE,
.revision = JAILHOUSE_CONFIG_REVISION,
.name = "core5-cell",
.flags = JAILHOUSE_CELL_VIRTUAL_CONSOLE_PERMITTED,
.cpu_set_size = sizeof(config.cpus),
.num_memory_regions = ARRAY_SIZE(config.mem_regions),
.num_cache_regions = ARRAY_SIZE(config.cache_regions),
.num_irqchips = 0,
.num_pio_regions = ARRAY_SIZE(config.pio_regions),
.num_pci_devices = 0,
.console = {
.type = JAILHOUSE_CON_TYPE_8250,
.flags = JAILHOUSE_CON_ACCESS_PIO,
.address = 0x3f8,
},
},
.cpus = {
0x20,
},
.mem_regions = {
/* RAM */ {
.phys_start = 0x57531180,
.virt_start = 0,
.size = 0x4c4b400,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,
},
/* communication region */ {
.virt_start = 0x4c4b400,
.size = 0x00001000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_COMM_REGION,
},
},
.cache_regions = {
{
.start = 0,
.size = 2,
.type = JAILHOUSE_CACHE_L3,
},
},
.pio_regions = {
PIO_RANGE(0x2f8, 8), /* serial 2 */
PIO_RANGE(0x3f8, 8), /* serial 1 */
PIO_RANGE(0xe010, 8), /* OXPCIe952 serial */
},
};
/*
* Jailhouse, a Linux-based partitioning hypervisor
*
* Copyright (c) Siemens AG, 2014-2017
*
* This work is licensed under the terms of the GNU GPL, version 2. See
* the COPYING file in the top-level directory.
*
* Alternatively, you can use or redistribute this file under the following
* BSD license:
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
* Configuration for QEMU Standard PC (Q35 + ICH9, 2009)
* created with '/usr/local/libexec/jailhouse/jailhouse config create -r data
sysconfig.c'
*
* NOTE: This config expects the following to be appended to your kernel cmdline
* "memmap=0x5200000$0x3a000000"
*/
#include <jailhouse/types.h>
#include <jailhouse/cell-config.h>
struct {
struct jailhouse_system header;
__u64 cpus[1];
struct jailhouse_memory mem_regions[13];
struct jailhouse_irqchip irqchips[1];
struct jailhouse_pio pio_regions[9];
struct jailhouse_pci_device pci_devices[7];
struct jailhouse_pci_capability pci_caps[3];
} __attribute__((packed)) config = {
.header = {
.signature = JAILHOUSE_SYSTEM_SIGNATURE,
.revision = JAILHOUSE_CONFIG_REVISION,
.flags = JAILHOUSE_SYS_VIRTUAL_DEBUG_CONSOLE,
.hypervisor_memory = {
.phys_start = 0x3a000000,
.size = 0x600000,
},
.debug_console = {
.address = 0x3f8,
.type = JAILHOUSE_CON_TYPE_8250,
.flags = JAILHOUSE_CON_ACCESS_PIO |
JAILHOUSE_CON_REGDIST_1,
},
.platform_info = {
.pci_mmconfig_base = 0xb0000000,
.pci_mmconfig_end_bus = 0xff,
.iommu_units = {
{
.type = JAILHOUSE_IOMMU_INTEL,
.base = 0xfed90000,
.size = 0x1000,
},
},
.x86 = {
.pm_timer_address = 0x608,
.vtd_interrupt_limit = 128,
},
},
.root_cell = {
.name = "RootCell",
.cpu_set_size = sizeof(config.cpus),
.num_memory_regions = ARRAY_SIZE(config.mem_regions),
.num_irqchips = ARRAY_SIZE(config.irqchips),
.num_pio_regions = ARRAY_SIZE(config.pio_regions),
.num_pci_devices = ARRAY_SIZE(config.pci_devices),
.num_pci_caps = ARRAY_SIZE(config.pci_caps),
},
},
.cpus = {
0x000000000000003f,
},
.mem_regions = {
/* MemRegion: 00000000-0009fbff : System RAM */
{
.phys_start = 0x0,
.virt_start = 0x0,
.size = 0xa0000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
/* MemRegion: 000f0000-000fffff : System ROM */
{
.phys_start = 0xf0000,
.virt_start = 0xf0000,
.size = 0x10000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: 00100000-39ffffff : System RAM */
{
.phys_start = 0x100000,
.virt_start = 0x100000,
.size = 0x39f00000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
/* MemRegion: 3f200000-7ffdefff : System RAM */
{
.phys_start = 0x3f200000,
.virt_start = 0x3f200000,
.size = 0x40ddf000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
/* MemRegion: fd000000-fdffffff : 0000:00:01.0 */
{
.phys_start = 0xfd000000,
.virt_start = 0xfd000000,
.size = 0x1000000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: feb80000-febbffff : 0000:00:02.0 */
{
.phys_start = 0xfeb80000,
.virt_start = 0xfeb80000,
.size = 0x40000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: febc0000-febdffff : e1000 */
{
.phys_start = 0xfebc0000,
.virt_start = 0xfebc0000,
.size = 0x20000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: febf0000-febf3fff : 0000:00:1b.0 */
{
.phys_start = 0xfebf0000,
.virt_start = 0xfebf0000,
.size = 0x4000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: febf4000-febf4fff : 0000:00:01.0 */
{
.phys_start = 0xfebf4000,
.virt_start = 0xfebf4000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: febf5000-febf5fff : 0000:00:1f.2 */
{
.phys_start = 0xfebf5000,
.virt_start = 0xfebf5000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fed00000-fed003ff : PNP0103:00 */
{
.phys_start = 0xfed00000,
.virt_start = 0xfed00000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: 000c0000-000dffff : ROMs */
{
.phys_start = 0xc0000,
.virt_start = 0xc0000,
.size = 0x20000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: 3a600000-3f1fffff : JAILHOUSE Inmate Memory */
{
.phys_start = 0x3a600000,
.virt_start = 0x3a600000,
.size = 0x4c00000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
},
.irqchips = {
/* IOAPIC 0, GSI base 0 */
{
.address = 0xfec00000,
.id = 0xff00,
.pin_bitmap = {
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
},
},
},
.pio_regions = {
/* Port I/O: 0000-001f : dma1 */
/* PIO_RANGE(0x0, 0x20), */
/* Port I/O: 0020-0021 : pic1 */
/* PIO_RANGE(0x20, 0x2), */
/* Port I/O: 0040-0043 : timer0 */
PIO_RANGE(0x40, 0x4),
/* Port I/O: 0050-0053 : timer1 */
/* PIO_RANGE(0x50, 0x4), */
/* Port I/O: 0060-0060 : keyboard */
PIO_RANGE(0x60, 0x1),
/* Port I/O: 0064-0064 : keyboard */
PIO_RANGE(0x64, 0x1),
/* Port I/O: 0070-0071 : rtc0 */
PIO_RANGE(0x70, 0x2),
/* Port I/O: 0080-008f : dma page reg */
/* PIO_RANGE(0x80, 0x10), */
/* Port I/O: 00a0-00a1 : pic2 */
/* PIO_RANGE(0xa0, 0x2), */
/* Port I/O: 00c0-00df : dma2 */
/* PIO_RANGE(0xc0, 0x20), */
/* Port I/O: 00f0-00ff : fpu */
/* PIO_RANGE(0xf0, 0x10), */
/* Port I/O: 02f8-02ff : serial */
PIO_RANGE(0x2f8, 0x8),
/* Port I/O: 03c0-03df : vga+ */
PIO_RANGE(0x3c0, 0x20),
/* Port I/O: 03e8-03ef : serial */
/* PIO_RANGE(0x3e8, 0x8), */
/* Port I/O: 03f8-03ff : serial */
PIO_RANGE(0x3f8, 0x8),
/* Port I/O: 0510-051b : QEMU0002:00 */
/* PIO_RANGE(0x510, 0xc), */
/* Port I/O: 0600-0603 : ACPI PM1a_EVT_BLK */
/* PIO_RANGE(0x600, 0x4), */
/* Port I/O: 0604-0605 : ACPI PM1a_CNT_BLK */
/* PIO_RANGE(0x604, 0x2), */
/* Port I/O: 0608-060b : ACPI PM_TMR */
/* PIO_RANGE(0x608, 0x4), */
/* Port I/O: 0620-062f : ACPI GPE0_BLK */
/* PIO_RANGE(0x620, 0x10), */
/* Port I/O: 0700-073f : 0000:00:1f.3 */
/* PIO_RANGE(0x700, 0x40), */
/* Port I/O: c000-c03f : 0000:00:02.0 */
PIO_RANGE(0xc000, 0x40),
/* Port I/O: c080-c09f : 0000:00:1f.2 */
PIO_RANGE(0xc080, 0x20),
},
.pci_devices = {
/* PCIDevice: 00:00.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x0,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:01.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x8,
.bar_mask = {
0xff000000, 0x00000000, 0xfffff000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:02.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x10,
.bar_mask = {
0xfffe0000, 0xffffffc0, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:1b.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xd8,
.bar_mask = {
0xffffc000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 1,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:1f.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xf8,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:1f.2 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xfa,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0xffffffe0, 0xfffff000,
},
.caps_start = 1,
.num_caps = 2,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:1f.3 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xfb,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0xffffffc0, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
},
.pci_caps = {
/* PCIDevice: 00:1b.0 */
{
.id = PCI_CAP_ID_MSI,
.start = 0x60,
.len = 0xe,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
/* PCIDevice: 00:1f.2 */
{
.id = PCI_CAP_ID_MSI,
.start = 0x80,
.len = 0xe,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_SATA,
.start = 0xa8,
.len = 0x2,
.flags = 0,
},
},
};
