On 30.09.21 09:07, Peng Fan (OSS) wrote:
> From: Peng Fan <[email protected]>
>
> With Linux Kernel 5.15
> commit 6abbd6988971a ("irqchip/gic, gic-v3: Make SGIs use
> handle_percpu_devid_irq()"),
> the on_each_cpu IPI_CALL_FUNC interrupt active flag will not be cleared
> until interrupt handler finish.
>
> Without Jailhouse hypervisor enabled, everything is ok, but when
> enabling jailhouse, HCR_EL2.[FMO | IMO] is set, that means NS-EL1
> is actually accessing ICV_DIR_EL1 when eoi_irq after enter_hypervisor
> return. It not able to deactive the interrupt that is actually a
> phyiscal irq which in active state.
>
> To ARM64, the IPI_CALL_FUNC is using SGI 1 which is same value as
> jailhouse SGI_EVENT.
>
> Then the following `jailhouse cell create` will hang the system, because
> the previous 'SGI_EVENT' is in active state and not deactivated, so
> the current SGI_EVENT issued not able to interrupt the target cpu core.
>
> To resolve this issue, let's clear the active bit of SGI_EVENT and
> SGI_INJECT before back to Linux.
>
> Tested on NXP i.MX8MP-EVK
>
> Signed-off-by: Peng Fan <[email protected]>
> ---
> hypervisor/arch/arm-common/gic-v3.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/hypervisor/arch/arm-common/gic-v3.c
> b/hypervisor/arch/arm-common/gic-v3.c
> index 03cface0..8327a95a 100644
> --- a/hypervisor/arch/arm-common/gic-v3.c
> +++ b/hypervisor/arch/arm-common/gic-v3.c
> @@ -200,7 +200,7 @@ static int gicv3_cpu_init(struct per_cpu *cpu_data)
> unsigned long redist_addr = system_config->platform_info.arm.gicr_base;
> unsigned long redist_size = GIC_V3_REDIST_SIZE;
> void *redist_base = gicr_base;
> - unsigned long gicr_ispendr;
> + unsigned long gicr_ispendr, gicr_isacter;
> unsigned int n;
> void *gicr;
> u64 typer, mpidr;
> @@ -291,6 +291,10 @@ static int gicv3_cpu_init(struct per_cpu *cpu_data)
> /* After this, the cells access the virtual interface of the GIC. */
> arm_write_sysreg(ICH_HCR_EL2, ICH_HCR_EN);
>
> + /* Clear SGI active flag */
> + gicr_isacter = mmio_read32(gicr + GICR_ISACTIVER);
> + mmio_write32(gicr + GICR_ICACTIVER, gicr_isacter & 0xffff);
> +
Do we also have to migrate this state into the virtual GIC?
Jan
> /* Forward any pending physical SGIs to the virtual queue. */
> gicr_ispendr = mmio_read32(gicr + GICR_ISPENDR);
> for (n = 0; n < 16; n++) {
>
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