On 01.10.21 15:17, Peng Fan wrote: > > > Jan Kiszka <[email protected] <mailto:[email protected]>>于2021年9月30日 > 周四下午4:54写道： > > On 30.09.21 09:07, Peng Fan (OSS) wrote: > > From: Peng Fan <[email protected] <mailto:[email protected]>> > > > > With Linux Kernel 5.15 > > commit 6abbd6988971a ("irqchip/gic, gic-v3: Make SGIs use > handle_percpu_devid_irq()"), > > the on_each_cpu IPI_CALL_FUNC interrupt active flag will not be > cleared > > until interrupt handler finish. > > > > Without Jailhouse hypervisor enabled, everything is ok, but when > > enabling jailhouse, HCR_EL2.[FMO | IMO] is set, that means NS-EL1 > > is actually accessing ICV_DIR_EL1 when eoi_irq after enter_hypervisor > > return. It not able to deactive the interrupt that is actually a > > phyiscal irq which in active state. > > > > To ARM64, the IPI_CALL_FUNC is using SGI 1 which is same value as > > jailhouse SGI_EVENT. > > > > Then the following `jailhouse cell create` will hang the system, > because > > the previous 'SGI_EVENT' is in active state and not deactivated, so > > the current SGI_EVENT issued not able to interrupt the target cpu > core. > > > > To resolve this issue, let's clear the active bit of SGI_EVENT and > > SGI_INJECT before back to Linux. > > > > Tested on NXP i.MX8MP-EVK > > > > Signed-off-by: Peng Fan <[email protected] <mailto:[email protected]>> > > --- > > hypervisor/arch/arm-common/gic-v3.c | 6 +++++- > > 1 file changed, 5 insertions(+), 1 deletion(-) > > > > diff --git a/hypervisor/arch/arm-common/gic-v3.c > b/hypervisor/arch/arm-common/gic-v3.c > > index 03cface0..8327a95a 100644 > > --- a/hypervisor/arch/arm-common/gic-v3.c > > +++ b/hypervisor/arch/arm-common/gic-v3.c > > @@ -200,7 +200,7 @@ static int gicv3_cpu_init(struct per_cpu > *cpu_data) > > unsigned long redist_addr = > system_config->platform_info.arm.gicr_base; > > unsigned long redist_size = GIC_V3_REDIST_SIZE; > > void *redist_base = gicr_base; > > - unsigned long gicr_ispendr; > > + unsigned long gicr_ispendr, gicr_isacter; > > unsigned int n; > > void *gicr; > > u64 typer, mpidr; > > @@ -291,6 +291,10 @@ static int gicv3_cpu_init(struct per_cpu > *cpu_data) > > /* After this, the cells access the virtual interface of the > GIC. */ > > arm_write_sysreg(ICH_HCR_EL2, ICH_HCR_EN); > > > > + /* Clear SGI active flag */ > > + gicr_isacter = mmio_read32(gicr + GICR_ISACTIVER); > > + mmio_write32(gicr + GICR_ICACTIVER, gicr_isacter & 0xffff); > > + > > Do we also have to migrate this state into the virtual GIC? > > > I think no need. And it will introduce complexity >
Likely right, the general interrupt mask will prevent that the root cell is seeing any unexpected nesting of SGIs. Applied both patches, just transplanting the inline comment from patch 2 to patch 1. Thanks, Jan -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/d/msgid/jailhouse-dev/017d4c43-657e-fb64-da41-9dfaceff48e7%40web.de.
